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Asynchronous Sram

repair — Sat, 27 Mar 2010 23:22:17 +0000

Static RAM, or SRAM, is the most basic and easy to use type of volatile memoryand is found in almost every computer in one form or another. An SRAM deviceis conceptually easy to understand, consisting of an array of latches along withcontrol and decode logic to resolve the address that is being read or written atany given time. Each latch is a feedback circuit that traps and maintains aparticular logic state. A typical SRAM bit implementation is shown in Fig. 4.7.

FIGURE 4.7 SRAM bit feedback latch.

An SRAM latch is created by connecting two inverters in a loop. One side of theloop remains sta- ble at the desired logic state, and the other remains stable at theopposite state. Inverters are used rather than noninverting buffers, because aninverter is the simplest logic element to construct. The two pass transistors oneither side of the latch enable both writing and reading. When writing, the transistorsturn on and force each half of the loop to whatever state is driven on the verticalbit lines. When reading, the transistors also turn on, but the bit lines are sensedrather than driven. Typical SRAM implementations require six transistors per bitof memory: two transistors for each inverter and the two pass transistors. Someimplementations use only a single transistor per inverter, requiring only fourtransistors per bit.
Discrete asynchronous SRAM devices have been around for decades. In the 1980s,the 6264 and 62256 were manufactured by multiple vendors and used in applicationsthat required simple RAM architectures with relatively quick access times and lowpower consumption. The 62xxx family is numbered according to its density inkilobits. Hence, the 6264 provides 65,536 bits of RAM ar- ranged as 8k ? 8.The 62256 provides 262,144 bits of RAM arranged as 32k ? 8. Beingmanufactured in CMOS technology and not using a clock, these devicesconsume very little power and draw only microamps when not being accessed.
The 62xxx family pin assignment is virtually identical to that of the 27xxx EPROMfamily, enabling system designs where either EPROM or SRAM can be substitutedinto the same location with only a couple of jumpers to set for unique signals suchas the program-enable on an EPROM or write-enable on an SRAM. Like anEPROM or basic ?ash device, asynchronous SRAMs have a simple interfaceconsisting of address, data, chip select, output enable, and write enable. Thisinterface is shown in Fig. 4.8.
Writes are performed whenever the WE* signal is held low. Therefore, one mustensure that the desired address and data are stable before asserting WE* andthat WE* is removed while address and data remain stable. Otherwise, thewrite may corrupt an undesired memory location. Unlike an EPROM, but like?ash, the data bus is bidirectional during normal operation. The ?rst twotransactions shown are writes as evidenced by the separate assertions ofWE* for the duration of address and data stability. As soon as the writesare completed, the microprocessor should release the data bus to thehigh-impedance state. When OE* is asserted, the SRAM begins driving thedata bus and the output re?ects the data contents at the locations speci?edon the address bus.
Asynchronous SRAMs are available with access times of less than 100 ns forinexpensive parts and down to 10 ns for more expensive devices. Access timemeasures both the maximum delay between a stable read address and itscorresponding data and the minimum duration of a write cycle. Their ease ofuse makes them suitable for small systems where megabytes of memory arenot re-quired and where reduced complexity and power consumption arekey requirements. Volatile memory doesnt get any simpler than asynchronousSRAM.
Prior to the widespread availability of ?ash, many computer designs in the 1980sutilized asyn- chronous SRAM with a battery backup as a means of implementingnonvolatile memory for storing con?guration information. Because an idle SRAMdraws only microamps of current, a small battery can maintain an SRAMscontents for several years while the main power is turned off. Using SRAM inthis manner has two distinct advantages over other technologies: writes arequick and easy, because there are no complex EEPROM or ?ash programmingalgorithms, and there is no limit to the number of write cycles performed overthe life of the product. The downsides to this approach are a lack of securityfor protecting valuable con?guration information and the need for a battery tomaintain the memory contents. Requiring a battery increases the complexity ofthe system and also begs the question of what happens when the battery wearsout. In the 1980s, it was common for a PCs BIOS con?guration to be storedin battery-backed CMOS SRAM. This is how terms like the CMOS andCMOS setup entered the lexicon of PC administration.

FIGURE 4.8 62xxx SRAM interface.

SRAM is implemented not only as discrete memory chips but is commonly foundintegrated within other types of chips, including microprocessors. Smallermicroprocessors or microcontrollers (microprocessors integrated with memoryand peripherals on a single chip) often contain a quantity of on-board SRAM.More complex microprocessors may contain on-chip data caches implementedwith SRAM.

By : E-book Complete_Digital_Design

Intel 8086 16-Bit Microprocessor Family

repair — Wed, 10 Mar 2010 09:11:54 +0000

Intel moved up to a 16-bit microprocessor, the 8086, in 1978 just two years afterintroducing the 8085 as an enhancement to the 8080. The x86 family is famousfor being chosen by IBM for their original PC. As PCs developed during thepast 20 years, the x86 family grew with the industry ?rst to 32 bits (80386,Pentium) and more recently to 64 bits (Itanium). While the 8086 was a newarchitecture, it retained certain architectural characteristics of the 8080/8085such that assembly language programs written for its predecessors could beconverted over to the 8086 with little or no modi?cation. This is one of thekey reasons for its initial success.
The 8086 contains various 16-bit registers as shown in Fig. 6.9, some of whichcan be manipu- lated one byte at a time. AX, BX, CX, and DX aregeneral-purpose registers that have alternate functions and that can be treatedas single 16-bit registers or as individual 8-bit registers. The accumulator,AX, and the ?ags register serve their familiar functions. BX can serve as ageneral pointer. CX is a loop iteration count register that is used inherentlyby certain instructions. DX is used as a companion register to AX whenperforming certain arithmetic operations such as integer division or handlinglong integers (32 bits).
The remaining registers are pointers of various types that index into the 8086ssomewhat awk- ward segmented memory structure. Despite being a 16-bitmicroprocessor with no register exceeding 16 bits in size, Intel recognized theneed for more than 64 kB of addressable memory in more advanced computers.One megabyte of memory space was decided upon as a suf?ciently largeaddress space in the late 1970s, but the question remained of how to accessthat memory with 16-bit pointers. Intels solution was to have programmersarbitrarily break the 1 MB address space into multiple 64-kB special-purposesegments one for instructions (code segment), two for data (primary data andextra data), and one for the stack. Memory operations must reference oneof these de?ned segments, requiring only a 16-bit pointer to address anylocation within a given segment. Segments can be located anywhere in memory,as shown in Fig. 6.10, and can be moved at will to provide ?exibility fordifferent applications. Additionally, there is no restriction on overlapping ofsegments.
Each segment register represents the upper 16 bits of a 20-bit pointer(220 = 1 MB) where the lower 4 bits are ?xed at 0. Therefore, a segment registerdirectly points to an arbitrary location in 1 MB of memory on a 16-byte boundary.A pointer register is then added to the 20-bit segment address to yield a ?nal20-bit address, the effective address, with which to fetch or store data.Algebraically, this relationship is expressed as: effective address =(segment pointer ? 16) + offset pointer.

FIGURE 6.9 8086 register set.

FIGURE 6.10 8086 segments.

Inside the microprocessor, this math is performed by shifting the segment pointer(0×135F) left by four bits and then adding the offset pointer (0×0102) asshown below.

This segmented addressing scheme has some awkward characteristics. First,programs must orga- nize their instructions and data into 64-kB chunks andproperly keep track of which portions are be- ing accessed. If data outsideof the current segments is desired, the appropriate segment register must beupdated. Second, the same memory location can be represented by multiplecombinations of segment and offset values, which can cause confusion in sortingout which instruction is accessing which location in memory. Nonetheless,programmers and the manufacturers of their development tools have ?guredout ways to avoid these traps and others like them.
Instructions that reference memory implicitly or explicitly determine whichoffset pointer is added to which segment register to yield the desired effectiveaddress. For example, a push or pop instruction inherently uses the stackpointer in combination with the stack segment register. However, an instructionto move data from memory to the accumulator can use one of multiple pointerregisters relative to any of the segment registers.
The 8086s reset and interrupt vectors are located at opposite ends of thememory space. On reset, the instruction pointer is set to 0xFFFF0, and themicroprocessor begins executing instructions from this address. Therefore,rather than being a true vector, the 16-byte reset region contains normalexecutable instructions. The interrupt vectors are located at the bottom ofthe memory space starting from address 0, and there are 256 vectors, onefor each of the 256 interrupt types. Each interrupt vector is composed of a2-byte segment address and a 2-byte offset address, from which a 20-biteffective address is calculated. When the 8086s INTR pin is driven high,an interrupt acknowledge process begins via the INTA* output pin. The8086 pulses INTA* low twice and, on the second pulse, the interruptingperipheral drives an interrupt type, or vector number, onto the eight lowerbits of the data bus. The vector number is used to index into the interruptvector table by multiplying it by 4 (shifting left by two bits), because each vectorconsists of four bytes. For example, interrupt type 0×03 would cause themicroprocessor to fetch four bytes from addresses 0×0C through 0×0F.Interrupts triggered by the INTR pin are all maskable via an internal control bit.Software can also trigger interrupts of various types via the INT instruction.A nonmaskable interrupt can be triggered by external hardware via the NMIpin. NMI initiates the type-2 interrupt service routine at the address indicatedby the vector at 0×08-0×0B.
Locating the reset boot code at the top of memory and the interrupt vectors atthe bottom often leads to an 8086 computer architecture with ROM at the topand some RAM at the bottom. ROM must be at the top, for obvious reasons.Placing the interrupt vector table in RAM enables a ?exible system in whichsoftware applications can install their own ISRs to perform various tasks. Onthe original IBM PC platform, it was not uncommon for programs to insert theirown ISR addresses into certain interrupt vectors located in RAM. The systemtimer and keyboard interrupts were common objects of this activity. Becausethe PCs operating system already implemented ISRs for these interrupts, theprogram could redirect the interrupt vector to its own ISR and then call thesystems default ISR when its own ISR completed execution. If properly done,this interrupt chaining process could add new features to a PC without harmingthe existing housekeeping chores performed by the standard ISRs. Chainingthe keyboard interrupt could enable a program that is normally dormant topop up each time a particular key sequence is pressed.
Despite its complexity and 16-bit processing capability, the 8086 was original lyhoused in a 40-pin DIP the same package used for most 8-bit processors of the time. Intel chose to use a multiplexed address/data scheme similar to that usedon the 8051 microcontroller, thereby saving 16 pins. The 8086s 20-bit addressbus is shared by the data bus on the lower 16 bits and by status ?ags on the upper 4 bits. Combined with additional signals, these status ?ags control the microprocessors bus interface. As with Intels other microprocessors, the 8086contains separate address spaces for memory and I/O devices. A control pinon the chip indicates whether a transaction is memory or I/O.
While the memory space is 1 MB in size, the I/O space is only 64 kB. The8086 bus interface oper- ates in one of two modes, minimum and maximum,determined by a control pin tied either high or low, respectively. In each ofthese two modes, many of the control and status pins take on different functions.In minimum mode, the control signals directly drive a standard Intel-style bussimilar to that of the 8080 and 8051, with read and write strobes and addresslatch enable. Other signals include a READY signal for inserting wait states forslow peripherals and a bus grant/acknowledge mechanism for supporting DMAor similar bus-sharing peripherals. Minimum mode is designed for smallersystems in which little address decoding logic is necessary to interface the 8086to memory and peripherals devices. Maximum mode is designed for largersystems where an Intel companion chip, the 8288 bus controller, integratesmore complex bus control logic onto an off-the-shelf IC. In maximum mode,certain status and control pins communicate more information about what typeof transaction is being performed at any given time, enabling the 8288 to takeappropriate action.
The 8086s 16-bit data bus is capable of transacting a single byte at a time forpurposes of access- ing byte-wide peripherals. One early advantage of the 8086was its backward bus compatibility with the 8080/8085. In the 1970s, Intelmanufactured a variety of I/O peripherals such as timers and parallel I/Odevices for their eight-bit microprocessors. The 8086s ability to performbyte-wide trans- actions enabled easy reuse of existing eight-bit peripheralproducts. Two signals, byte high enable (BHE*) and address bit zero (A[0]),communicate the width and active byte of each bus transaction as shown inTable 6.3.

Intels microprocessors follow the little-endian byte ordering convention.Little-endian refers to the practice of locating the LSB of a multibyte quantity ina lower address and the MSB in a higher address. In a little-endian 16-bitmicroprocessor, the value 0×1234 would be stored in memory by locating 0×12into address 1 and 0×34 into address 0. Big-endian is the opposite: locating theLSB in the higher address and the MSB in the lower address. Therefore, abig-endian 16-bit microprocessor would store 0×12 into address 0 and 0×34into address 1. To clarify the difference, Table 6.4 shows little-endian versusbig-endian for 16- and 32-bit quantities as viewed from a memory chipsperspective. Here, ADDR represents the base address of a multibyte dataelement.
Proponents of little-endian argue that it makes better sense, because the lowbyte goes into the low address. Proponents of big-endian argue that it makes better sense, because data is stored in memory as you would read and interpret it. Thechoice of endianness is rather religious and comes down to personal preference.Of course, if you are designing with a little-endian microprocessor, life will bemade simpler to maintain the endianness consistently throughout the system.

At the time of the 8086s introduction, 16-bit desktop computer systems werealmost unheard of and could be substantially more expensive than 8-bit systemsas a result of the increased memory size required to support the larger bus. Toalleviate this problem and speed market acceptance of its architecture, Intelintroduced the 8088 microprocessor in 1979, which was essentially an 8086with an eight-bit data bus. A lower-cost computer system could be built with the8088, because fewer EPROM and RAM chips were necessary, system logicdid not have to deal with two bytes at a time, and less circuit board wiring wasrequired. A tremendous bene?t to Intel in designing the 8088 was the factthat it was chosen by IBM as the low-cost 16-bit heart of the original PC/XTdesktop computer, thereby locking the x86 microprocessor family into theIBM PC architecture for decades to come.
A variety of companion chips were developed by Intel to supplement the8086/8088. Among these was the 8087 math coprocessor that enhanced the 8086scomputational capabilities with ?oating-point arithmetic operations. Floating-pointarithmetic refers to a computers handling of real numbers as compared to integers.The task of adding or multiplying two real numbers of arbitrary magnitude is farmore complex than similar integer operations. Certain applications such as scienti?csimulations and realistic games that construct a virtual reality world make signi?cantuse of ?oating-point operations. The 8087 is a coprocessor rather than a peripheral,because it sits on the microprocessor bus in parallel with the 8086 and watches forspecial ?oating-point instructions.
These instructions are then executed automatically by the 8087 rather than havingto wait for the 8086 to request an operation. The 8086 was designed with the 8087sexistence in mind and ignores instructions destined for the 8087. Therefore, softwaremust speci?cally know if a math coprocessor is installed to run correctly. Manyprograms that ran on older systems with or without a coprocessor would ?rst testto see if the coprocessor was installed and then execute either an optimized set ofroutines for the 8087 or a slower set of routines that emulated the ?oating-pointoperations via conventional 8086 instructions.
As the x86 family developed, the optional math coprocessor was eventuallyintegrated alongside the integer processor on the same silicon chip. The 8087 gaveway to the 80287 and 80387 when the 80286 and 80386 microprocessors wereproduced. When Intel introduced the 80486, the coprocessor, or ?oating-pointunit (FPU), was integrated on chip. This integration resulted in a somewhat moreexpensive product, so Intel released a lower-cost 80486SX microprocessorwithout the coprocessor. An 80487SX was made available to upgrade systemsoriginally sold with the 80486SX chips, but the overall situation provedsomewhat chaotic with various permutations of microprocessors and systemswith and without coprocessors. Starting with the Pentium, all of Intels high-endmicroprocessors contain integrated FPUs. This trend is not unique to Intel.High-performance microprocessors in general began integrating the FPU atroughly the same time because of the performance bene?ts and the overallsimplicity of placing the microprocessor and FPU onto the same chip.

By : E-book Complete_Digital_Design

Motorola 6800 Eight -Bit Microprocessor Family

repair — Sat, 06 Mar 2010 21:27:32 +0000

As the microprocessor market began to take off, Motorola jumped into the frayand introduced its eight-bit 6800 in 1974, shortly after the 8080 ?rst appeared.While no longer available as a discrete microprocessor, the 6800 is signi?cant,because it remains in Motorolas successful 68HC05/68HC08 and 68HC11microcontroller families and also serves as a vehicle with which to learn thebasics of computer architecture. Like the 8080, the 6800 is housed in a 40-pinDIP and features a 16-bit address bus and an 8-bit data bus. All of the basicregister types of a modern microprocessor are implemented in the 6800, asshown in Fig. 6.1: a program counter (PC), stack pointer (SP), index register(X), two general-purpose accumulators (ACCA and ACCB), and status?ags set by the ALU in the condition code register (CCR). ACCA is theprimary accumulator, and some instructions oper- ate only on this registerand not ACCB. A half-carry ?ag is included to enable ef?cient binary codeddecimal (BCD) operations. After adding two BCD values with normal binaryarithmetic, the half- carry is used to convert illegal results back to BCD. The6800 provides a special instruction, decimal adjust ACCA (DAA), for thisspeci?c purpose. A somewhat out-of-place interrupt mask bit is alsoimplemented in the CCR, because this was an architecturally convenient placeto locate it. Bits in the CCR are modi?ed through either ALU operations ordirectly by transferring the value in ACCA to the CCR.
The 6800 supports three interrupts: one nonmaskable, one maskable, andone software interrupt. More recent variants of the 6800 support additionalinterrupt sources. A software interrupt can be used by any program runningon the microprocessor to immediately jump to some type of maintenanceroutine whose address does not have to be known by the calling program.When the software interrupt instruction is executed, the 6800 reads theappropriate interrupt vector from memory and jumps to the indicated address.The 6800s reset and interrupt vectors are located at the top of memory, aslisted in Table 6.1, which generally dictates that the boot ROM be locatedthere as well. For example, an 8-kB 27C64 EPROM(8,192 bytes = 0×2000 bytes) would occupy the address range 0xE000through 0xFFFF. Each vector is 16 bits wide, enough to specify the fulladdress of the associated routine. The MSB of the address, A[15:8], islocated in the low, or even, byte address, and the LSB, A[7:0] is locatedin the high, or odd, byte address.

FIGURE 6.1 6800 registers.

An external clock driver circuit that provides a two-phase clock (two clocksignals 180? out of phase with respect to each other) is required for the original6800. Motorola simpli?ed the design of 6800-based computer systems byintroducing two variants, the 6802 and 6808. The 6802 includes an on-boardclock driver circuit of the type that is now standard on many microprocessorsavailable today. Such clock drivers require only an external crystal to createa stable, reliable oscillator with which to clock the microprocessor. A crystalis a two-leaded component that contains a specially cut quartz crystal.The quartz can be made to resonate at its natural frequency by electricalstimulus cre- ated within the microprocessors on-board clock driver circuitry.A crystal is necessary for this pur- pose, because its oscillation frequency ispredictable and stable. The 6802 also includes 128 bytes of on-board RAMto further simplify certain systems that have small volatile memory requirements.For customers who wanted the simpli?ed clocking scheme of the 6802without paying for the on-board RAM, Motorolas 6808 kept the clockingand removed the RAM.
Using a 6802 with its internal RAM, a functional computer could be constructedwith only two chips: the 6802 and an EPROM. Unfortunately, such a computerwould not be very useful, because it would have no I/O with which to interactwith the outside world. Motorola manufactured a variety of peripheral chipsintended for direct connection to the 6800 bus. Among these were the 6821peripheral interface adapter (PIA) and the 6850 asynchronous communicationsinterface adapter (ACIA), a type of UART. The PIA provides 20 I/O signalsarranged as two 8-bit parallel ports, each with two control signals. Applicationsincluding basic pushbutton sensing and LED driving are easy with the 6821.The 6800 bus uses asynchronous control signals, meaning that memory andI/O devices do not explicitly require access to the microprocessor clock tocommunicate on the bus. However, many of the 6800 peripherals requiretheir own copy of the clock to run internal logic.
As with all synchronous logic, the 6800s bus is internally controlled by themicroprocessor clock, but the nature of the control signals enables asynchronousread and write transactions without referencing that clock, as shown in Fig. 6.2.An address is placed onto the bus along with the proper state of the R/Wselect signal (read = 1, write = 0) and a valid memory address (VMA) enablethat indicates an active bus cycle. In the case of a write, the write data isdriven out some time later. For reads, the data must be returned fast enoughto meet the microprocessors timing speci?cations. The 6802/6808 weremanufactured in 1-, 1.5-, and 2-MHz speed grades. At 2 MHz, a peripheraldevice has to respond to a read request with valid data within 210 ns afterthe assertion of address, R/W, and VMA. A peripheral has up to 290 nsfrom the assertion of these signals to complete a write transaction.
*In a real system, VMA, combined with address decoding logic, would drivethe individual chip select signals to each peripheral.
In some situations, slow peripherals may be used that cannot execute a bustransaction in the time allowed by the microprocessor. The 6800 architecturedeals with this by stretching the clock during a slow bus cycle. A clockcycle can be stretched as long as 10 ?s, enabling extremely slow peripheralsby delaying the next clock edge that will advance the microprocessorsinternal state and termi- nate a pending bus cycle. This stretching isperformed by an external clock circuit for a 6800, or by the internal clockof the 6802/6808. As with many modern microprocessors, the 6802/6808provides a pin that delays the end of the current bus cycle. This memoryready (MR) signal is normally high, signaling that the addressed device isready. When brought low, the clock is internally stretched until MR goeshigh again. Early microprocessors such as the 6800 used clock stretchingto delay bus cy- cles. Most modern microprocessors maintain a constantclock frequency and, instead, insert discrete wait states, or extra clockcycles, into a bus transaction when a similar type of signal is asserted.This latter method is usually preferable in a synchronous system becauseof the desire to maintain a simple clock circuit and to not disrupt otherlogic that may be running on the microprocessor clock.

FIGURE 6.2 6802/6808 basic bus timing.

Motorolas success with the 6800 motivated it to introduce the upgraded 6809in 1978. The 6809 is instruction set compatible with the 6800 but includesseveral new registers that enable more ?exi- ble access to memory. Two stackpointers are present: the existing hardware controlled register for subroutinecalls and interrupts, and another for user control. The user stack pointer canbe used to ef?ciently pass parameters to subroutines as they are called withoutcon?icting with the microprocessors push/pop operations involving theprogram counter and other registers. A second index register and the abilityto use any of the four 16-bit pointer registers as index registers were addedto enable the simultaneous handling of multiple data structure pointers withouthaving to continually save and recall index register values. The 6809s twoaccumulators can be concatenated to form a 16-bit accumulator that enables16-bit arithmetic with an enhanced ALU. This ALU is also capable of eight-bitunsigned multiplication, which made the 6809 one of the ?rst integratedmicroprocessors with multiplication capability.
Other improvements in the 6809 included a direct page register (DPR) for amore ?exible eight- bit direct addressing mode. The 8-bit DPR, representingA[15:8], is combined with an 8-bit direct address, representing A[7:0], toform a 16-bit direct address, thereby enabling an 8-bit direct address toreference any location in the complete 64-kB address space. The 6809 alsoincluded a more advanced bus interface with direct support for an externalDMA controller. Several desktop computers, including the Tandy/RadioShack TRS-80 Color Computer, and various platforms, including arcadegames, utilized the 6809.
While still available from odd-lot retail outlets, the original 6800 family membersare no longer practical to use in many computing applications. Their capabilities,once leading edge, are now available in smaller, more integrated ICs at lowercost and with lower power consumption. However, the 6800 architecture isalive and well in the 68HC05/68HC08 and 68HC11 microcontroller familiesthat are based on the 6800/6802/6808 and 6809 architectures, respectively.These microcontrollers are available with a wide range of integrated featureswith on-board RAM, ROM (mask ROM, EE-PROM, or EPROM), serialports, timers, and analog-to-digital converters.

By : E-book Complete_Digital_Design

Assembly Language And Addressing Modes

repair — Mon, 15 Feb 2010 01:09:16 +0000

With the hardware ready, a computer requires software to make it more than an
inactive collection of components. Microprocessors fetch instructions from program
memory, each consisting of an opcode and, optionally, additional operands following
the opcode. These opcodes are binary data that are easy for the microprocessor to
decode, but they are not very readable by a person. To enable a programmer to
more easily write software, an instruction representation called assembly language
was developed. Assembly language is a low-level language that directly represents
each binary opcode with a human-readable text mnemonic. For example, the
mnemonic for an unconditional branch-to-subroutine instruction could be BSR.
In contrast, a high-level language such as C++ or Java contains more complex
logical expressions that may be automatically converted by a compiler to dozens
of microprocessor instructions. Assembly language programs are assembled,
rather than compiled, into opcodes by directly translating each mnemonic into
its binary equivalent.

Assembly language also makes programming easier by enabling the usage of
text labels in place of hard-coded addresses. A subroutine can be named FOO,
and when BSR FOO is encountered by the assembler, a suitable branch target
address will be automatically calculated in place of the label FOO. Each type of
assembler requires a slightly different format and syntax, but there are general
assembly language conventions that enable a programmer to quickly adapt to
speci?c implementations once the basics are understood. An assembly language
program listing usually has three columns of text followed by an optional comment
column as shown in Fig. 3.14. The ?rst column is for labels that are placeholders
for addresses to be resolved by the assembler. Instruction mnemonics are located
in the second column. The third column is for instruction operands.

This listing uses the Motorola 6800 familys assembly language format. Though
developed in the 1970s, 68xx microprocessors are still used today in embedded
applications such as automobiles and industrial automation. The ?rst line of this
listing is not an instruction, but an assembler directive that tells the assembler to
locate the program at memory location $100. When assembled, the listing is
converted into a memory dump that lists a range of memory addresses and
their corresponding contents opcodes and operands. Assembler directives
are often indicated with a period pre?x. The program in Fig. 3.14 is very simple:
it counts to 30 ($1E) and then sends the Z character out the serial port. It
continues in an in?nite loop by returning to the start of the program when the
serial port routine has completed its task. The subroutine to handle the serial
port is not shown and is referenced with the SEND_CHAR label. The program
begins by clearing accumulator A (the 6800 has two accumulators: ACCA and
ACCB). It then enters an incrementing loop where the accumulator is incremented
and then compared against the terminal count value, $1E. The # pre?x tells the
assembler to use the literal value $1E for the comparison. Other alternatives are
possible and will soon be discussed. If ACCA is unequal to $1E, the
microprocessor goes back to increment ACCA. If equal, the accumulator is
loaded with the ASCII character to be transmitted, also a literal operand.
The assumption here is that the SEND_CHAR subroutine transmits whatever
is in ACCA. When the subroutine ?nishes, the program starts over with the
branch-always instruction.

Each of the instructions in the preceding program contains at least one operand.
CLRA and INCA have only one operand: ACCA. CMPA and LDAA each have
two operands: ACCA and associated data. Complex microprocessors may
reference three or more operands in a single instruction. Some instructions can
reference different types of operands according to the requirements of the program
being implemented. Both CMPA and LDAA reference literal operands in this
example, but a pro- grammer cannot always specify a predetermined literal data
value directly in the instruction sequence. Operands can be referenced in a
variety of manners, called addressing modes, depending on the type of instruction
and the type of operand. Some types of instructions inherently use only one
addressing mode, and some types have multiple modes. The manners of
referencing operands can be categorized into six basic addressing modes: implied,
immediate, direct, relative, indirect, and indexed. To fully understand how a
microprocessor works, and to ef?ciently utilize an instruction set, it is
necessary to explore the various mechanisms used to reference data.

Implied addressing speci?es the operand of an instruction as an inherent property
of that instruction. For example, CLRA implies the accumulator by de?nition.
No additional addressing information following the opcode is needed.

FIGURE 3.14 Typical assembly language listing.

Immediate addressing places an operands value literally into the instruction
sequence. LDAA#Z has its primary operand immediately available following the
opcode. An immediate oper-and is indicated with the # pre?x in some assembly
languages. Eight-bit microprocessors with eight-bit instruction words cannot ?t an
immediate value into the instruction word itself and, therefore, require that an
extra byte following the opcode be used to specify the immediate value. More
powerful 32-bit microprocessors can often ?t a 16-bit or 24-bit immediate value
within the instruction word. This saves an additional memory fetch to obtain the
operand.

Direct addressing places the address of an operand directly into the instruction
sequence. Instead of specifying LDAA #Z, the programmer could specify
LDAA $1234. This version of the instruction would tell the microprocessor to
read memory location $1234 and load the resulting value into the accumulator.
The operand is directly available by looking into the memory address speci?ed
just following the instruction. Direct addressing is useful when there is a need to
read a ?xed memory location. Usage of the direct addressing mode has a slightly
different impact on various microprocessors. A typical 8-bit microprocessor has a
16-bit address space, meaning that two bytes following the opcode are necessary
to represent a direct address. The 8-bit microprocessor will have to perform two
additional 8-bit fetch operations to load the direct address. A typical 32-bit
microprocessor has a 32-bit address space, meaning that 4 bytes following the
opcode are necessary. If the 32-bit microprocessor has a 32-bit data bus, only
one additional 32-bit fetch operation is required to load the direct address.

Relative addressing places an operands relative address into the instruction
sequence. A relative address is expressed as a signed offset relative to the current
value of the PC. Relative addressing is often used by branch instructions, because
the target of a branch is usually within a short distance of the PC, or current
instruction. For example, BNE INC_LOOP results in a branch-if-not-equal
backward by two instructions. The assembler automatically resolves the addresses
and calculates a relative offset to be placed following the BNE opcode. This
relative operation is performed by adding the offset to the PC. The new PC value
is then used to resume the instruction fetch and execution process. Relative
addressing can utilize both positive and negative deltas that are applied to the
PC. A microprocessors instruction format constrains the relative range that can
be speci?ed in this addressing mode. For example, most 8-bit microprocessors
provide only an 8-bit signed ?eld for relative branches, indicating a range
of +127/128 bytes. The relative delta value is stored into its own byte just
after the opcode. Many 32-bit microprocessors allow a 16-bit delta ?eld and
are able to ?t this value into the 32-bit instruction word, enabling the entire
instruction to be fetched in a single memory read. Limiting the range of a
relative operation is generally not an excessive constraint because of
softwares locality property. Locality in this context means that the set of
instructions involved in performing a speci?c task are generally relatively
close together in memory. The locality property covers the great majority of
branch instructions. For those few branches that have their targets outside of
the allowed relative range, it is necessary to perform a short relative branch to
a long jump instruction that speci?es a direct address. This reduces the
ef?ciency of the microprocessor by having to perform two branches when
only one is ideally desired, but the overall ef?ciency of saving extra memory
accesses for the majority of short branches is worth the trade-off.

Indirect addressing speci?es an operands direct address as a value contained
in another register. The other register becomes a pointer to the desired data. For
example, a microprocessor with two accumulators can load ACCA with the
value that is at the address in ACCB. LDAA (ACCB) would tell the
microprocessor to put the value of accumulator B onto the address bus,
perform a read, and put the returned value into accumulator A. Indirect
addressing allows writing software routines that operate on data at different
addresses. If a programmer wants to read or write an arbitrary entry in a data
table, the software can load the address of that entry into a microprocessor
register and then perform an indirect access using that register as a pointer.
Some microprocessors place constraints on which registers can be used as
references for indirect addressing. In the case of a 6800 microprocessor,
LDAA (ACCB) is not actually a supported operation but serves as a
syntactical example for purposes of discussion.

Indexed addressing is a close relative (no pun intended) of indirect addressing,
because it also refers to an address contained in another register. However,
indexed addressing also speci?es an off-set, or index, to be added to that
register base value to generate the ?nal operand address:

base + offset = ?nal address.

Some microprocessors allow general accumulator registers to be used as
base-address registers, but others, such as the 6800, provide special index
registers for this purpose. In many 8-bit microprocessors, a full 16-bit address
cannot be obtained from an 8-bit accumulator serving as the base address.
Therefore, one or more separate index registers are present for the purpose
of indexed addressing. In contrast, many 32-bit microprocessors are able to
specify a full 32-bit address with any general-purpose register and place no
limitations on which register serves as the index register. Indexed addressing
builds upon the capabilities of indirect addressing by enabling multiple address
offsets to be referenced from the same base address. LDAA (X+$20) would
tell the microprocessor to add $20 to the index register, X, and use the
resulting address to fetch data to be loaded into ACCA. One simple example
of using indexed addressing is a subroutine to add a set of four numbers
located at an arbitrary location in memory. Before calling the subroutine, the
main program can set an index register to point to the table of numbers. Within
the subroutine, four individual addition instructions use the indexed addressing
mode to add the locations X+0, X+1, X+2, and X+3. When so written, the
subroutine is ?exible enough to be used for any such set of numbers. Because
of the similarity of indexed and indirect addressing, some microprocessors
merge them into a single mode and obtain indirect addressing by performing
indexed addressing with an index value of zero.

The six conceptual addressing modes discussed above represent the various
logical mechanisms that a microprocessor can employ to access data. It is
important to realize that each individual microprocessor applies these addressing
modes differently. Some combine multiple modes into a single mode (e.g.,
indexed and indirect), and some will create multiple submodes out of a single
mode. The exact variation depends on the speci?cs of an individual
microprocessors architecture.

With the various addressing modes modifying the speci?c opcode and operands
that are presented to the microprocessor, the bene?ts of using assembly language
over direct binary values can be observed. The programmer does not have to
worry about calculating branch target addresses or resolving different addressing
modes. Each mnemonic can map to several unique opcodes, depending on
the addressing mode used. For example, the LDAA instruction in Fig. 3.14 could
easily have used extended addressing by specifying a full 16-bit address at which
the ASCII transmit-value is located. Extended addressing is the 6800s mechanism
for specifying a 16-bit direct address. (The 6800s direct addressing involves only
an eight-bit address.) In either case, the assembler would determine the correct
opcode to represent LDAA and insert the correct binary values into the memory
dump. Additionally, because labels are resolved each time the program is
assembled, small changes to the program can be made that add or remove
instructions and labels, and the assembler will automatically adjust the resulting
addresses accordingly.

Programming in assembly language is different from using a high-level language,
because one must think in smaller steps and have direct knowledge about the
microprocessors operation and architecture. Assembly language is processor-
speci?c instead of generic, as with a high-level language. Therefore, assembly
language programming is usually restricted to special cases such as boot code
or routines in which absolute ef?ciency and performance are demanded.
A human programmer will usually be able to write more ef?cient assembly
language than a high-level language compiler can generate. In large programs,
the slight inef?ciency of the compiler is well worth the trade-off for ease of
programming in a high-level language. However, time-critical routines such
as I/O drivers or ISRs may bene?t from manual assembly language coding.

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Address Banking

repair — Thu, 11 Feb 2010 13:01:19 +0000

A microprocessors address space is normally limited by the width of its address
bus, but supplemental logic can greatly expand address space, subject to certain
limitations. Address banking is a technique that increases the amount of memory
a microprocessor can address. If an application requires 1 MB of RAM for
storing large data structures, and an 8-bit microprocessor is used with a 64-kB
address space, address banking can enable the microprocessor to access the full
1 MB one small section at a time.

Address banking, also known as paging, takes a large quantity of memory, divides
it into multiple smaller banks, and makes each bank available to the microprocessor
one at a time. A bank address register is maintained by the microprocessor and
determines which bank of memory is selected at any given time. The selected
bank is accessed through a portion of the microprocessors ?xed address space,
called a window, set aside for banked memory access. As shown in Fig. 3.10a,
the upper 16 kB of address space provides direct access to one of many 16-kB
pages in the larger banked memory structure. Figure 3.10b shows the logical
implementation of this banked memory scheme. A 22-bit combined address is
sent to the 4-MB banked memory structure: 256 pages ? 16 kB per page
= 4 MB. These 22 bits are formed through the concatenation of the 8-bit bank
address register and 14 of the microprocessors low-order address bits, A[13:0].
The eight bank-address bits are changed infrequently whenever the
microprocessor is ready for a new page in memory. The 14 microprocessor-
address bits can change each time the window is accessed.

FIGURE 3.10 Address banking.

The details of a banking scheme can be modi?ed according to the applications
requirements. The bank access window can be increased or decreased, and more
or fewer pages can be de?ned. If an application operates on many small sets of
data, a larger number of smaller pages may be suitable. If the data or software
set is widely dispersed, it may be better to increase the window size as much as
possible to minimize the bank address register update rate.

While address banking can greatly increase the memory available to a
microprocessor, it does so with the penalties of increased access time on page
switches and more complexity in managing the segmented address space.
Each time the microprocessor wants to access a location in a different page,
it must update the bank address register. This penalty is acceptable in some
applications. How- ever, if the application requires both consistently fast
access time and large memory size, a faster, more expensive microprocessor
may be required that suits these needs.

The complexity of managing the segmented address space dissuades some
engineers from em- ploying address banking. Software usually bears the brunt
of recognizing when necessary data re- sides in a different page and then
updating the bank address register to access that page. It is easier for
software to deal with a large, continuous address space. With the easy
availability and low cost of 32-bit microprocessors, address banking is not
as common as it used to be. However, if an 8-bit microprocessor must be
used for cost reduction or other limitations, address banking may be useful
when memory demands increase beyond 64 kB.

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Implementation of An Eight-Bit Computer

repair — Wed, 10 Feb 2010 11:05:27 +0000

Having discussed some of the basic principles of microprocessor architecture and
operation, we can examine how a microprocessor ?ts into a system to form a computer.
Microprocessors need external memory in which to store their programs and the data
upon which they operate. In this context, ex- ternal memory is viewed from a logical
perspective. That is, the memory is always external to the core microprocessor
element. Some processor chips on the market actually contain a certain quantity of
memory within them, but, logically speaking, this memory is still external to the actual
microprocessor core.

In the general sense, a computer requires a quantity of nonvolatile memory, or
ROM, in which to store the boot code that will be executed on reset. The ROM
may contain all or some of the micro- processors full set of software. A small
embedded computer, such as the one in a microwave oven, contains all its software
in ROM. A desktop computer contains very little of its software in ROM. A
computer also requires a quantity of volatile memory, or RAM, that can be used
to store data associated with the various tasks running on the computer. RAM
is where the microprocessors stack is lo- cated. Additionally, RAM can be used
to hold software that is loaded from an external source.

For purposes of discussion, consider the basic eight-bit computer shown in Fig. 3.7
with a small quantity of memory and a serial port with which to communicate with
the outside world. Eight kilobytes of ROM is suf?cient to store boot code and
software, including a serial communications program. Eight kilobytes of RAM is
suf?cient to hold data associated with the ROM software, and it also enables
loading additional software not already included in the ROM. The control signals
in this hypothetical computer are active-low, as are the control signals in most
computer designs that, according to convention, have been in widespread use
for the past few decades. Active-low signal names have some type of symbol
as a pre?x or suf?x to the signal name that distinguishes them from active-high
signals. Common symbols used for this purpose include #, *, , and _. From a
logical perspective, it is perfectly valid to use active-high signaling. However,
because most memory and peripheral devices conform to the active-low
convention, it is often easier to go along with the established convention.

FIGURE 3.7 Eight-bit computer block diagram.

While hypothetical, the microprocessor shown contains characteristics that are
common in off- the-shelf eight-bit microprocessors. It contains an 8-bit data
bus and a 16-bit address bus with a total address space of 64 kB. The
combined MPU bus, consisting of address, data, and control signals, is
asynchronous and is enabled by the assertion of read and write enable signals.
When the micropro- cessor wants to read a location in memory, it asserts the
appropriate address along with RD* and then takes the resulting value driven
onto the data bus. As shown in the diagram, memory chips usually have
output enable (OE*) signals that can be connected to a read enable. Such
devices continuously decode the address bus and will emit data whenever
OE* is active.

Not all 64 kB of address space is used in this computer. Address decoding logic
breaks the single 64-kB space into four 16-kB regions. According to the state
of A[15:14], one and only one of the chip select signals is activated. The address
decoding follows the truth table shown in Table 3.1 and establishes four
address ranges.

Once decoded into regions, A[13:0] provides unique address information to the
memory and I/O devices connected to the MPU bus. One memory region, the
upper 16 kB, is currently left unused. It may be used in the future if more memory
or another I/O device is added. Each memory and I/O device has a chip select
input and will respond to a read or write command only when that select signal
is active. Furthermore, each chip, including the microprocessor, contains internal
tri-state buffers to prevent contention on the bus. The tri-state buffers are not
enabled unless the chips select signal is active and a read is being performed
(a write, in the case of the microprocessor). Without external address decoding,
none of these chips can share an address region with any other devices, because
they do not have enough address bits to fully decode the entire 16-bit address bus.

Not all address bits are used by the memory and serial port chips. The ROM
and RAM are each only 8k in size. Therefore, only 13 address bits, A[12:0],
are required and, as a result, A[13] is left unconnected. The serial port has far
fewer memory locations and therefore uses only A[3:0], for a maximum of
16 unique addresses.

When a device does not utilize all of the address bits that have been allocated for
its particular address region, the potential for aliasing exists. The ROM occupies
only 8k (13 bits) of the 16k (14 bits) address region. Therefore, the ROM has
no knowledge of any additional addresses above 8k: the region from 0×2000
to 0×3FFFF. What happens if the MPU tries to read location 0×2000? 0×2000
differs from 0×0000 only in the state of A[13]. Because the ROM does not have
any knowledge of A[13], it interprets 0×2000 to be 0×0000. In other words,
0×2000 aliases to 0×0000. Similarly, the entire upper 8k of the address region
aliases to the lower 8k. In the case of the serial port controller, there is a greater
degree of aliasing, because the serial port only uses A[3:0]. This means that there
can be only 16 unique address locations in the entire 16k region. These 16 locations
will therefore appear to be replicated 210 = 1,024 times as indicated by the ten
unused address bits, A[13:4].

As long as the software is properly written to understand the computers memory
map, it will properly access the memory locations that are available and will
avoid aliased portions of the memory map. Aliasing is not a problem in itself but
can lead to problems if software does not access memory and peripherals in
the way in which the hardware engineer intended. If software is written for
the hypothetical computer with the incorrect assumption that 16 kB of RAM
is present, data may be unwittingly corrupted when addresses between 0×6000
and 0×7FFF are written, because they will alias to 0×4000-0×5FFF and
overwrite any existing data.

When the MPU wants to read data from a particular memory location, it asserts
that address onto A[15:0]. This causes the address decoder to update its chip
select outputs, which enables the appro- priate memory chip or the serial port.
After allowing time for the chip select to propagate, the RD* signal is asserted,
and the WR* signal is left unasserted. This informs the selected device that a read
is requested. The device is then able to drive the data bus, D[7:0], with the
requested data. After allowing some time for the read data to be driven, the
MPU captures the data and releases the RD* sig- nal, ending the read request.
The sequence of events, or timing, for the read transaction is shown in Fig. 3.8.

This type of MPU bus is asynchronous, because its sequence of events is not
driven by a clock but rather by the assertion and removal of the various signals
that are timed relative to one another by the MPU and the devices with which it
is communicating. For this interface to work properly, the MPU must allow
enough time for the read to occur, regardless of the speci?c device with which
it is com- municating. In other words, it must operate according to the capabilities
of the slowest device the least common denominator.

FIGURE 3.8 MPU read timing.

Write timing is very similar, as seen in Fig. 3.9. Again, the MPU asserts the desired
address onto A[15:0], and the appropriate chip select is decoded. At the same time,
the write data is driven onto D[7:0]. Once the address and data have had time to
stabilize, and after allowing time for the chip select to propagate, the WR* enable
signal is asserted to actually trigger the write. The WR* signal is de-asserted while
data, address, and chip select are still stable so that there is no possibility of writing
to a different location and corrupting data. If the WR* signal is de-asserted at the
same time as the others, a race condition could develop wherein a particular
device may sense the address (or data or chip select) change just prior to WR*
changing, resulting in a false write to another location or to the current location
with wrong data. Being an asynchronous interface, the duration of all signal as-
sertions must be suf?cient for all devices to properly execute the write.

An MPU interrupt signal is asserted by the serial port controller to enable easier
programming of the serial port communication routine. Rather than having software
continually poll the serial port to see if data are waiting, the controller is con?gured
to assert INTR* whenever a new byte arrives. The MPU is then able to invoke
an ISR, which can transfer the data byte from the serial port to the RAM. The
interrupt also helps when transmitting data, because the speed of the typical
serial port (often 9,600 to 38,400 bps) is very slow as compared to the clock
speed of even a slow MPU (1 to 10 MHz). When the software wants to send a
set of bytes out the serial port, it must send one byte and then wait a relatively
long time until the serial port is ready for the next byte. Instead of polling in a loop
between bytes, the serial port controller asserts INTR* when it is time to send the
next byte. The ISR can then respond with the next byte and return control to the
main program that is run- ning at the time. Each time INTR* is asserted and the
ISR responds, the ISR must be sure to clear the interrupt condition in the serial
port. Depending on the exact serial port device, a read or write to a speci?c
register will clear the interrupt. If the interrupt is not cleared before the ISR
issues a return-from-interrupt, the MPU may be falsely interrupted again for
the same condition.

FIGURE 3.9 MPU write timing.

This computer contains two other functional elements: the clock and reset circuits.
The 1-MHz clock must be supplied to the MPU continually for proper operation.
In this example design, no other components in the computer require this clock.
For fairly simple computers, this is a realistic scenario, because the buses and
memory devices operate asynchronously. Many other computers, however, have
synchronous buses, and the microprocessor clock must be distributed to other
components in the system.

The reset circuit exists to start the MPU when the system is ?rst turned on. Reset
must be applied for a certain minimum duration after the power supply has
stabilized. This is to ensure that the digital circuits properly settle to known
states before they are released from reset and allowed to begin normal
operation. As the computer is turned on, the reset circuit actively drives the
RST* signal. Once power has stabilized, RST* is de-asserted and remains
in this state inde?nitely.

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