Generating Boolean equations to implement a desired logic function is a necessary
step before a circuit can be implemented. Truth tables are a common means of
describing logical relationships between Boolean inputs and outputs. Once a truth
table has been created, it is not always easy to convert that truth table directly into
a Boolean equation. This translation becomes more dif?cult as the number of
variables in a function increases. A graphical means of translating a truth table into a
logic equation was invented by Maurice Karnaugh in the early 1950s and today is
called the Karnaugh map, or K-map. A K-map is a type of truth table drawn such
that individual product terms can be picked out and summed with other product
terms extracted from the map to yield an overall Boolean equation. The best way
to explain how this process works is through an example. Consider the
hypothetical logical relationship in Table 1.6.

If the corresponding Boolean equation does not immediately become clear, the
truth table can be converted into a K-map as shown in Fig. 1.3. The K-map has
one box for every combination of inputs, and the desired output for a given
combination is written into the corresponding box. Each axis of a K-map represents
up to two variables, enabling a K-map to solve a function of up to four variables.
Individual grid locations on each axis are labeled with a unique combination of the
variables represented on that axis. The labeling pattern is important, because only
one variable per axis is permitted to differ between adjacent boxes. Therefore,
the pattern 00, 01, 10, 11 is not proper, but the pattern 11, 01, 00, 10
would work as well as the pattern shown.

K-maps are solved using the sum of products principle, which states that any relationship
can be expressed by the logical OR of one or more AND terms. Product terms in a
K-map are recognized by picking out groups of adjacent boxes that all have a state of 1.
The simplest product term is a single box with a 1 in it, and that term is the product of
all variables in the K-map with each variable either inverted or not inverted such that
the result is 1. For example, a 1 is observed in the box that corresponds to A = 0, B = 1,
and C = 1. The product term representation of that box would be ABC. A brute force
solution is to sum together as many product terms as there are boxes with a state of 1
(there are ?ve in this example) and then simplify the resulting equation to obtain the ?nal
result. This approach can be taken without going to the trouble of drawing a K-map.
The purpose of a K-map is to help in identifying minimized product terms so that lengthy
simpli?cation steps are unnecessary. Minimized product terms are identi?ed by
grouping together as many adjacent boxes with a state of 1 as possible, subject to the
rules of Boolean algebra. Keep in mind that, to generate a valid product term, all boxes
in a group must have an identical relationship to all of the equations input variables.
This requirement translates into a rule that product term groups must be found in
power-of-two quantities. For a three-variable K-map, product term groups can have
only 1, 2, 4, or 8 boxes in them.

Going back to our example, a four-box product term is formed by grouping together
the vertically stacked 1s on the left and right edges of the K-map. An interesting aspect
of a K-map is that an edge wraps around to the other side, because the axis labeling
pattern remains continuous. The validity of this wrapping concept is shown by the
fact that all four boxes share a common relationship with the input variables: their
product term is B. The other variables, A and C, can be ruled out, because the
boxes are 1 regardless of the state of A and C. Only variable B is a determining factor,
and it must be 0 for the boxes to have a state of 1. Once a product term has been
identi?ed, it is marked by drawing a ring around it as shown in Fig. 1.4. Because
the product term crosses the edges of the table, halfrings are shown in the appropriate
locations.

There is still a box with a 1 in it that has not yet been accounted for. One approach
could be to generate a product term for that single box, but this would not result in
a fully simpli?ed equation, because a larger group can be formed by associating the
lone box with the adjacent box corresponding to A = 0, B = 0, and C = 1. K-map
boxes can be part of multiple groups, and forming the largest groups possible results
in a fully simpli?ed equation. This second group of boxes is circled in Fig. 1.5 to
complete the map. This product term shares a common relationship where
A = 0, C = 1, and B

FIGURE 1.3 Karnaugh map for function of three variables.

FIGURE 1.4 Partially completed Karnaugh map for a function of three variables.

is irrelevant: It may appear tempting to create a product term consisting of the three
boxes on the bottom edge of the K-map. This is not valid because it does not result
in all boxes sharing a common product relationship, and therefore violates the
power-of-two rule mentioned previously. Upon completing the K-map, all product
terms are summed to yield a ?nal and simpli?ed Boolean equation that relates the
input variables and the output:

Having discussed some of the basic principles of microprocessor architecture and
operation, we can examine how a microprocessor ?ts into a system to form a computer.
Microprocessors need external memory in which to store their programs and the data
upon which they operate. In this context, ex- ternal memory is viewed from a logical
perspective. That is, the memory is always external to the core microprocessor
element. Some processor chips on the market actually contain a certain quantity of
memory within them, but, logically speaking, this memory is still external to the actual
microprocessor core.

In the general sense, a computer requires a quantity of nonvolatile memory, or
ROM, in which to store the boot code that will be executed on reset. The ROM
may contain all or some of the micro- processors full set of software. A small
embedded computer, such as the one in a microwave oven, contains all its software
in ROM. A desktop computer contains very little of its software in ROM. A
computer also requires a quantity of volatile memory, or RAM, that can be used
to store data associated with the various tasks running on the computer. RAM
is where the microprocessors stack is lo- cated. Additionally, RAM can be used
to hold software that is loaded from an external source.

For purposes of discussion, consider the basic eight-bit computer shown in Fig. 3.7
with a small quantity of memory and a serial port with which to communicate with
the outside world. Eight kilobytes of ROM is suf?cient to store boot code and
software, including a serial communications program. Eight kilobytes of RAM is
suf?cient to hold data associated with the ROM software, and it also enables
loading additional software not already included in the ROM. The control signals
in this hypothetical computer are active-low, as are the control signals in most
computer designs that, according to convention, have been in widespread use
for the past few decades. Active-low signal names have some type of symbol
as a pre?x or suf?x to the signal name that distinguishes them from active-high
signals. Common symbols used for this purpose include #, *, , and _. From a
logical perspective, it is perfectly valid to use active-high signaling. However,
because most memory and peripheral devices conform to the active-low
convention, it is often easier to go along with the established convention.

FIGURE 3.7 Eight-bit computer block diagram.

While hypothetical, the microprocessor shown contains characteristics that are
common in off- the-shelf eight-bit microprocessors. It contains an 8-bit data
bus and a 16-bit address bus with a total address space of 64 kB. The
combined MPU bus, consisting of address, data, and control signals, is
asynchronous and is enabled by the assertion of read and write enable signals.
When the micropro- cessor wants to read a location in memory, it asserts the
appropriate address along with RD* and then takes the resulting value driven
onto the data bus. As shown in the diagram, memory chips usually have
output enable (OE*) signals that can be connected to a read enable. Such
devices continuously decode the address bus and will emit data whenever
OE* is active.

Not all 64 kB of address space is used in this computer. Address decoding logic
breaks the single 64-kB space into four 16-kB regions. According to the state
of A[15:14], one and only one of the chip select signals is activated. The address
decoding follows the truth table shown in Table 3.1 and establishes four
address ranges.

Once decoded into regions, A[13:0] provides unique address information to the
memory and I/O devices connected to the MPU bus. One memory region, the
upper 16 kB, is currently left unused. It may be used in the future if more memory
or another I/O device is added. Each memory and I/O device has a chip select
input and will respond to a read or write command only when that select signal
is active. Furthermore, each chip, including the microprocessor, contains internal
tri-state buffers to prevent contention on the bus. The tri-state buffers are not
enabled unless the chips select signal is active and a read is being performed
(a write, in the case of the microprocessor). Without external address decoding,
none of these chips can share an address region with any other devices, because
they do not have enough address bits to fully decode the entire 16-bit address bus.

Not all address bits are used by the memory and serial port chips. The ROM
and RAM are each only 8k in size. Therefore, only 13 address bits, A[12:0],
are required and, as a result, A[13] is left unconnected. The serial port has far
fewer memory locations and therefore uses only A[3:0], for a maximum of
16 unique addresses.

When a device does not utilize all of the address bits that have been allocated for
its particular address region, the potential for aliasing exists. The ROM occupies
only 8k (13 bits) of the 16k (14 bits) address region. Therefore, the ROM has
no knowledge of any additional addresses above 8k: the region from 0×2000
to 0×3FFFF. What happens if the MPU tries to read location 0×2000? 0×2000
differs from 0×0000 only in the state of A[13]. Because the ROM does not have
any knowledge of A[13], it interprets 0×2000 to be 0×0000. In other words,
0×2000 aliases to 0×0000. Similarly, the entire upper 8k of the address region
aliases to the lower 8k. In the case of the serial port controller, there is a greater
degree of aliasing, because the serial port only uses A[3:0]. This means that there
can be only 16 unique address locations in the entire 16k region. These 16 locations
will therefore appear to be replicated 210 = 1,024 times as indicated by the ten
unused address bits, A[13:4].

As long as the software is properly written to understand the computers memory
map, it will properly access the memory locations that are available and will
avoid aliased portions of the memory map. Aliasing is not a problem in itself but
can lead to problems if software does not access memory and peripherals in
the way in which the hardware engineer intended. If software is written for
the hypothetical computer with the incorrect assumption that 16 kB of RAM
is present, data may be unwittingly corrupted when addresses between 0×6000
and 0×7FFF are written, because they will alias to 0×4000-0×5FFF and
overwrite any existing data.

When the MPU wants to read data from a particular memory location, it asserts
that address onto A[15:0]. This causes the address decoder to update its chip
select outputs, which enables the appro- priate memory chip or the serial port.
After allowing time for the chip select to propagate, the RD* signal is asserted,
and the WR* signal is left unasserted. This informs the selected device that a read
is requested. The device is then able to drive the data bus, D[7:0], with the
requested data. After allowing some time for the read data to be driven, the
MPU captures the data and releases the RD* sig- nal, ending the read request.
The sequence of events, or timing, for the read transaction is shown in Fig. 3.8.

This type of MPU bus is asynchronous, because its sequence of events is not
driven by a clock but rather by the assertion and removal of the various signals
that are timed relative to one another by the MPU and the devices with which it
is communicating. For this interface to work properly, the MPU must allow
enough time for the read to occur, regardless of the speci?c device with which
it is com- municating. In other words, it must operate according to the capabilities
of the slowest device the least common denominator.

FIGURE 3.8 MPU read timing.

Write timing is very similar, as seen in Fig. 3.9. Again, the MPU asserts the desired
address onto A[15:0], and the appropriate chip select is decoded. At the same time,
the write data is driven onto D[7:0]. Once the address and data have had time to
stabilize, and after allowing time for the chip select to propagate, the WR* enable
signal is asserted to actually trigger the write. The WR* signal is de-asserted while
data, address, and chip select are still stable so that there is no possibility of writing
to a different location and corrupting data. If the WR* signal is de-asserted at the
same time as the others, a race condition could develop wherein a particular
device may sense the address (or data or chip select) change just prior to WR*
changing, resulting in a false write to another location or to the current location
with wrong data. Being an asynchronous interface, the duration of all signal as-
sertions must be suf?cient for all devices to properly execute the write.

An MPU interrupt signal is asserted by the serial port controller to enable easier
programming of the serial port communication routine. Rather than having software
continually poll the serial port to see if data are waiting, the controller is con?gured
to assert INTR* whenever a new byte arrives. The MPU is then able to invoke
an ISR, which can transfer the data byte from the serial port to the RAM. The
interrupt also helps when transmitting data, because the speed of the typical
serial port (often 9,600 to 38,400 bps) is very slow as compared to the clock
speed of even a slow MPU (1 to 10 MHz). When the software wants to send a
set of bytes out the serial port, it must send one byte and then wait a relatively
long time until the serial port is ready for the next byte. Instead of polling in a loop
between bytes, the serial port controller asserts INTR* when it is time to send the
next byte. The ISR can then respond with the next byte and return control to the
main program that is run- ning at the time. Each time INTR* is asserted and the
ISR responds, the ISR must be sure to clear the interrupt condition in the serial
port. Depending on the exact serial port device, a read or write to a speci?c
register will clear the interrupt. If the interrupt is not cleared before the ISR
issues a return-from-interrupt, the MPU may be falsely interrupted again for
the same condition.

FIGURE 3.9 MPU write timing.

This computer contains two other functional elements: the clock and reset circuits.
The 1-MHz clock must be supplied to the MPU continually for proper operation.
In this example design, no other components in the computer require this clock.
For fairly simple computers, this is a realistic scenario, because the buses and
memory devices operate asynchronously. Many other computers, however, have
synchronous buses, and the microprocessor clock must be distributed to other
components in the system.

The reset circuit exists to start the MPU when the system is ?rst turned on. Reset
must be applied for a certain minimum duration after the power supply has
stabilized. This is to ensure that the digital circuits properly settle to known
states before they are released from reset and allowed to begin normal
operation. As the computer is turned on, the reset circuit actively drives the
RST* signal. Once power has stabilized, RST* is de-asserted and remains
in this state inde?nitely.

By : E-book Complete_Digital_Design

All solid materials deform when forces are applied to them, but often it is
reasonable to model components and structures as rigid bodies, at least
in the early part of the analysis. The forces on a rigid body are generally
not concurrent at the center of mass of the body, which cannot be
modeled as a particle if the force system tends to cause a rotation of the
body.

Moment of a Force

The turning effect of a force on a body is called the moment of the force,
or torque. The moment MA of a force F about a point A is de?ned
as a scalar quantity

M_A  = Fd            (1.2.7)

where d (the moment arm or lever arm) is the nearest distance from A
to the line of action of F. This nearest distance may be dif?cult to
determine in a three-dimensional scalar analysis; a vector method
is needed in that case.

Equivalent Forces

Sometimes the equivalence of two forces must be established for
simplifying the solution of a problem. The necessary and suf?cient
conditions for the equivalence of forces F  and F? are that they have the
same magnitude, direction, line of action, and moment on a given
rigid body in static equilibrium. Thus,

F = F’  and M_A  = M’_A

For example, the ball joint A in Figure 1.2.7 experiences the same
moment whether the vertical force is pushing or pulling downward
on the yoke pin.

FIGURE 1.2.7 Schematic of testing a ball joint of a car.

Vector Product of Two Vectors

A powerful method of vector mechanics is available for solving complex
problems, such as the moment of a force in three dimensions. The
vector product (or cross product) of two concurrent vectors A and
B is de?ned as the vector V = A ? B with the following properties:
1. V is perpendicular to the plane of vectors A and B.
2. The sense of V is given by the right-hand rule (Figure 1.2.8).
3. The magnitude of V is V = AB sin?, where ? is the angle between A and B.
4. A ? B ? B ? A, but A ? B = (B ? A).
5. For three vectors, A ? (B + C) = A ? B + A ? C.

FIGURE 1.2.8 Right-hand rule for vector products.

The vector product is calculated using a determinant,

Moment of a Force about a Point

The vector product is very useful in determining the moment of a force F
about an arbitrary point O. The vector de?nition of moment is

M_{0 ^{= r x F}}

where r is the position vector from point O to any point on the line of action
of F. A double arrow is often used to denote a moment vector in graphics.
The moment MO may have three scalar components, Mx, My, Mz, which
represent the turning effect of the force F about the corresponding
coordinate axes. In other words, a single force has only one moment about
a given point, but this moment may have up to three components with
respect to a coordinate system,

M_o = M_xi + M_yj + M_zk

Top

By : E-book Mechanical_Engineering_Handbook