Shkurt 28, 2010
Clock Skew
Postuar nga: riparim : Kategori: Digital Logic
The preceding timing analysis example is simpli?ed for ease of presentation byassuming that the source and destination ?ops in a logic path are driven by thesame clock signal. Although a synchro- nous circuit uses a common clock forall ?ops, there are small, nonzero variances in clock timing at individual ?ops.Wiring delay variances are one source of this nonideal behavior. When a clocksource drives two ?ops, the two wires that connect to each ?ops clock input areusually not identical
Figura 1.16 Hypothetical logic circuit.
in length. This length inequality causes one ?ops clock to arrive slightly before orafter the other ?ops clock.
Clock skew is the term used to characterize differences in edge timing betweenmultiple clock inputs. Skew caused by wiring delay variance can be effectivelyminimized by designing a circuit so that clock distribution wires are matched in length.A more troublesome source of clock skew arises when there are too many clockloads to be driven by a single source. Multiple clock drivers are necessary in thesesituations, with small variations in electrical characteristics between each driver.These driver variances result in clock skew across all the ?ops in a synchronousdesign. As might be expected, clock skew usually reduces the frequency at whicha synchronous circuit can operate. Clock skew is subtracted from the nominalclock period for setup time analysis purposes, because the worst-case scenarioshown in Fig. 1.17 must be considered. This scenario uses the same logic circuit inFig. 1.16 but shows two separate clocks with 1 ns of skew between them.
The worst timing occurs when the destination ?ops clock arrives before that of thesource ?op, thereby reducing the amount of time available for the D-input to stabilize.Instead of the circuit having zero margin with a 20-ns period, clock skew increasesthe minimum period to 21 ns. The extra 1 ns compensates for the clock skew torestore a minimum source to destination period time of 20 ns. A slower circuitsuch as this one is not very sensitive to clock skew, especially after backing off to40 MHz for timing margin as shown previously. Digital systems that run at relativelylow frequencies may not be affected by clock skew, because they often havesubstantial margins built into their timing analyses. As clock speeds increase, themargin decreases to the point at which clock skew and interconnect delay becomeimportant limiting factors in system design.
Hold time compliance can become more dif?cult in the presence of clock skew.The basic problem occurs when clock skew reduces the source ?ops apparent tCOfrom the destination ?ops perspective, causing the destinations input to changebefore tH is satis?dhe. Such problems are more prone in high-speed systems,but slower systems are not immune. Figura 1.18 shows a timing diagram for acircuit with 1 ns of clock skew where two ?ops are connected by a short wirewith nearly zero propagation delay. The ?ops have tCO = 2 ns and tH = 1.5 ns.A scenario like this may be expe- rienced when connecting two chips that arenext to each other on a circuit board. In the absence of clock skew, thedestination ?ops input would change tCO after the rising clock edge, exceeding tHby 0.5 ns. The worst-case clock skew causes the source ?op clock to arrivebefore that of the destination ?op, resulting in an input change just 1 ns after therising clock edge and violating tH. Solutions to skew-induced tH violations includereducing the skew or increasing the delay be- tween source and destination.Unfortunately, increasing a signals propagation delay may cause tSUviolations in high-speed systems.
Clock skew is the term used to characterize differences in edge timing betweenmultiple clock inputs. Skew caused by wiring delay variance can be effectivelyminimized by designing a circuit so that clock distribution wires are matched in length.A more troublesome source of clock skew arises when there are too many clockloads to be driven by a single source. Multiple clock drivers are necessary in thesesituations, with small variations in electrical characteristics between each driver.These driver variances result in clock skew across all the ?ops in a synchronousdesign. As might be expected, clock skew usually reduces the frequency at whicha synchronous circuit can operate. Clock skew is subtracted from the nominalclock period for setup time analysis purposes, because the worst-case scenarioshown in Fig. 1.17 must be considered. This scenario uses the same logic circuit inFig. 1.16 but shows two separate clocks with 1 ns of skew between them.
The worst timing occurs when the destination ?ops clock arrives before that of thesource ?op, thereby reducing the amount of time available for the D-input to stabilize.Instead of the circuit having zero margin with a 20-ns period, clock skew increasesthe minimum period to 21 ns. The extra 1 ns compensates for the clock skew torestore a minimum source to destination period time of 20 ns. A slower circuitsuch as this one is not very sensitive to clock skew, especially after backing off to40 MHz for timing margin as shown previously. Digital systems that run at relativelylow frequencies may not be affected by clock skew, because they often havesubstantial margins built into their timing analyses. As clock speeds increase, themargin decreases to the point at which clock skew and interconnect delay becomeimportant limiting factors in system design.
Hold time compliance can become more dif?cult in the presence of clock skew.The basic problem occurs when clock skew reduces the source ?ops apparent tCOfrom the destination ?ops perspective, causing the destinations input to changebefore tH is satis?dhe. Such problems are more prone in high-speed systems,but slower systems are not immune. Figura 1.18 shows a timing diagram for acircuit with 1 ns of clock skew where two ?ops are connected by a short wirewith nearly zero propagation delay. The ?ops have tCO = 2 ns and tH = 1.5 ns.A scenario like this may be expe- rienced when connecting two chips that arenext to each other on a circuit board. In the absence of clock skew, thedestination ?ops input would change tCO after the rising clock edge, exceeding tHby 0.5 ns. The worst-case clock skew causes the source ?op clock to arrivebefore that of the destination ?op, resulting in an input change just 1 ns after therising clock edge and violating tH. Solutions to skew-induced tH violations includereducing the skew or increasing the delay be- tween source and destination.Unfortunately, increasing a signals propagation delay may cause tSUviolations in high-speed systems.
Figura 1.17 Clock skew in?uence on setup time analysis.
Figura 1.18 Hold-time violation caused by clock skew.
Hold time may not be a problem in slower circuits, because slower circuits oftenhave paths between ?ops with suf?ciently long propagation delays to offsetclock skew problems. megjithatë, even slow circuits can experience hold-timeproblems if ?ops are connected with wires or components that have smallpropagation delays. It is also important to remember that hold-time complianceis not a function of clock period but of clock skew, tCO, and tH. Prandaj, aslow system that uses fast components may have problems if the clock skewexceeds the difference between tCO and tH.
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