Március 06, 2010
Motorola 6800 Eight -Bit Microprocessor Family
Írta:: javítás : Kategória: Tanulságos mikroprocesszorok és Microcomputer
As the microprocessor market began to take off, Motorola jumped into the frayand introduced its eight-bit 6800 in 1974, shortly after the 8080 ?rst appeared.While no longer available as a discrete microprocessor, A 6800 is signi?cant,because it remains in Motorolas successful 68HC05/68HC08 and 68HC11microcontroller families and also serves as a vehicle with which to learn thebasics of computer architecture. Like the 8080, A 6800 is housed in a 40-pinDIP and features a 16-bit address bus and an 8-bit data bus. All of the basicregister types of a modern microprocessor are implemented in the 6800, asshown in Fig. 6.1: a program counter (PC), stack pointer (SP), index register(X), two general-purpose accumulators (ACCA and ACCB), and status?ags set by the ALU in the condition code register (CCR). ACCA is theprimary accumulator, and some instructions oper- ate only on this registerand not ACCB. A half-carry ?ag is included to enable ef?cient binary codeddecimal (BCD) operations. After adding two BCD values with normal binaryarithmetic, the half- carry is used to convert illegal results back to BCD. A6800 provides a special instruction, decimal adjust ACCA (DAA), for thisspeci?c purpose. A somewhat out-of-place interrupt mask bit is alsoimplemented in the CCR, because this was an architecturally convenient placeto locate it. Bits in the CCR are modi?ed through either ALU operations ordirectly by transferring the value in ACCA to the CCR.
A 6800 supports three interrupts: one nonmaskable, one maskable, andone software interrupt. More recent variants of the 6800 support additionalinterrupt sources. A software interrupt can be used by any program runningon the microprocessor to immediately jump to some type of maintenanceroutine whose address does not have to be known by the calling program.When the software interrupt instruction is executed, A 6800 reads theappropriate interrupt vector from memory and jumps to the indicated address.The 6800s reset and interrupt vectors are located at the top of memory, aslisted in Table 6.1, which generally dictates that the boot ROM be locatedthere as well. For example, an 8-kB 27C64 EPROM(8,192 bytes = 0×2000 bytes) would occupy the address range 0xE000through 0xFFFF. Each vector is 16 bits wide, enough to specify the fulladdress of the associated routine. The MSB of the address, A[15:8], islocated in the low, or even, byte address, and the LSB, A[7:0] is locatedin the high, or odd, byte address.
A 6800 supports three interrupts: one nonmaskable, one maskable, andone software interrupt. More recent variants of the 6800 support additionalinterrupt sources. A software interrupt can be used by any program runningon the microprocessor to immediately jump to some type of maintenanceroutine whose address does not have to be known by the calling program.When the software interrupt instruction is executed, A 6800 reads theappropriate interrupt vector from memory and jumps to the indicated address.The 6800s reset and interrupt vectors are located at the top of memory, aslisted in Table 6.1, which generally dictates that the boot ROM be locatedthere as well. For example, an 8-kB 27C64 EPROM(8,192 bytes = 0×2000 bytes) would occupy the address range 0xE000through 0xFFFF. Each vector is 16 bits wide, enough to specify the fulladdress of the associated routine. The MSB of the address, A[15:8], islocated in the low, or even, byte address, and the LSB, A[7:0] is locatedin the high, or odd, byte address.
FIGURE 6.1 6800 registers.
An external clock driver circuit that provides a two-phase clock (two clocksignals 180? out of phase with respect to each other) is required for the original6800. Motorola simpli?ed the design of 6800-based computer systems byintroducing two variants, A 6802 és 6808. A 6802 includes an on-boardclock driver circuit of the type that is now standard on many microprocessorsavailable today. Such clock drivers require only an external crystal to createa stable, reliable oscillator with which to clock the microprocessor. A crystalis a two-leaded component that contains a specially cut quartz crystal.The quartz can be made to resonate at its natural frequency by electricalstimulus cre- ated within the microprocessors on-board clock driver circuitry.A crystal is necessary for this pur- pose, because its oscillation frequency ispredictable and stable. A 6802 also includes 128 bytes of on-board RAMto further simplify certain systems that have small volatile memory requirements.For customers who wanted the simpli?ed clocking scheme of the 6802without paying for the on-board RAM, Motorolas 6808 kept the clockingand removed the RAM.
Using a 6802 with its internal RAM, a functional computer could be constructedwith only two chips: A 6802 and an EPROM. Unfortunately, such a computerwould not be very useful, because it would have no I/O with which to interactwith the outside world. Motorola manufactured a variety of peripheral chipsintended for direct connection to the 6800 bus. Among these were the 6821peripheral interface adapter (PIA) and the 6850 asynchronous communicationsinterface adapter (ACIA), a type of UART. The PIA provides 20 I/O signalsarranged as two 8-bit parallel ports, each with two control signals. Applicationsincluding basic pushbutton sensing and LED driving are easy with the 6821.The 6800 bus uses asynchronous control signals, meaning that memory andI/O devices do not explicitly require access to the microprocessor clock tocommunicate on the bus. However, many of the 6800 peripherals requiretheir own copy of the clock to run internal logic.
As with all synchronous logic, the 6800s bus is internally controlled by themicroprocessor clock, but the nature of the control signals enables asynchronousread and write transactions without referencing that clock, as shown in Fig. 6.2.An address is placed onto the bus along with the proper state of the R/Wselect signal (read = 1, write = 0) and a valid memory address (VMA) enablethat indicates an active bus cycle. In the case of a write, the write data isdriven out some time later. For reads, the data must be returned fast enoughto meet the microprocessors timing speci?cations. A 6802/6808 weremanufactured in 1-, 1.5-, and 2-MHz speed grades. At 2 MHz, a peripheraldevice has to respond to a read request with valid data within 210 ns afterthe assertion of address, R/W, and VMA. A peripheral has up to 290 nsfrom the assertion of these signals to complete a write transaction.
*In a real system, VMA, combined with address decoding logic, would drivethe individual chip select signals to each peripheral.
In some situations, slow peripherals may be used that cannot execute a bustransaction in the time allowed by the microprocessor. A 6800 architecturedeals with this by stretching the clock during a slow bus cycle. A clockcycle can be stretched as long as 10 ?s, enabling extremely slow peripheralsby delaying the next clock edge that will advance the microprocessorsinternal state and termi- nate a pending bus cycle. This stretching isperformed by an external clock circuit for a 6800, or by the internal clockof the 6802/6808. As with many modern microprocessors, the 6802/6808provides a pin that delays the end of the current bus cycle. This memoryready (MR) signal is normally high, signaling that the addressed device isready. When brought low, the clock is internally stretched until MR goeshigh again. Early microprocessors such as the 6800 used clock stretchingto delay bus cy- cles. Most modern microprocessors maintain a constantclock frequency and, Helyette, insert discrete wait states, or extra clockcycles, into a bus transaction when a similar type of signal is asserted.This latter method is usually preferable in a synchronous system becauseof the desire to maintain a simple clock circuit and to not disrupt otherlogic that may be running on the microprocessor clock.
Using a 6802 with its internal RAM, a functional computer could be constructedwith only two chips: A 6802 and an EPROM. Unfortunately, such a computerwould not be very useful, because it would have no I/O with which to interactwith the outside world. Motorola manufactured a variety of peripheral chipsintended for direct connection to the 6800 bus. Among these were the 6821peripheral interface adapter (PIA) and the 6850 asynchronous communicationsinterface adapter (ACIA), a type of UART. The PIA provides 20 I/O signalsarranged as two 8-bit parallel ports, each with two control signals. Applicationsincluding basic pushbutton sensing and LED driving are easy with the 6821.The 6800 bus uses asynchronous control signals, meaning that memory andI/O devices do not explicitly require access to the microprocessor clock tocommunicate on the bus. However, many of the 6800 peripherals requiretheir own copy of the clock to run internal logic.
As with all synchronous logic, the 6800s bus is internally controlled by themicroprocessor clock, but the nature of the control signals enables asynchronousread and write transactions without referencing that clock, as shown in Fig. 6.2.An address is placed onto the bus along with the proper state of the R/Wselect signal (read = 1, write = 0) and a valid memory address (VMA) enablethat indicates an active bus cycle. In the case of a write, the write data isdriven out some time later. For reads, the data must be returned fast enoughto meet the microprocessors timing speci?cations. A 6802/6808 weremanufactured in 1-, 1.5-, and 2-MHz speed grades. At 2 MHz, a peripheraldevice has to respond to a read request with valid data within 210 ns afterthe assertion of address, R/W, and VMA. A peripheral has up to 290 nsfrom the assertion of these signals to complete a write transaction.
*In a real system, VMA, combined with address decoding logic, would drivethe individual chip select signals to each peripheral.
In some situations, slow peripherals may be used that cannot execute a bustransaction in the time allowed by the microprocessor. A 6800 architecturedeals with this by stretching the clock during a slow bus cycle. A clockcycle can be stretched as long as 10 ?s, enabling extremely slow peripheralsby delaying the next clock edge that will advance the microprocessorsinternal state and termi- nate a pending bus cycle. This stretching isperformed by an external clock circuit for a 6800, or by the internal clockof the 6802/6808. As with many modern microprocessors, the 6802/6808provides a pin that delays the end of the current bus cycle. This memoryready (MR) signal is normally high, signaling that the addressed device isready. When brought low, the clock is internally stretched until MR goeshigh again. Early microprocessors such as the 6800 used clock stretchingto delay bus cy- cles. Most modern microprocessors maintain a constantclock frequency and, Helyette, insert discrete wait states, or extra clockcycles, into a bus transaction when a similar type of signal is asserted.This latter method is usually preferable in a synchronous system becauseof the desire to maintain a simple clock circuit and to not disrupt otherlogic that may be running on the microprocessor clock.
FIGURE 6.2 6802/6808 basic bus timing.
Motorolas success with the 6800 motivated it to introduce the upgraded 6809in 1978. A 6809 is instruction set compatible with the 6800 but includesseveral new registers that enable more ?exi- ble access to memory. Two stackpointers are present: the existing hardware controlled register for subroutinecalls and interrupts, and another for user control. The user stack pointer canbe used to ef?ciently pass parameters to subroutines as they are called withoutcon?icting with the microprocessors push/pop operations involving theprogram counter and other registers. A second index register and the abilityto use any of the four 16-bit pointer registers as index registers were addedto enable the simultaneous handling of multiple data structure pointers withouthaving to continually save and recall index register values. The 6809s twoaccumulators can be concatenated to form a 16-bit accumulator that enables16-bit arithmetic with an enhanced ALU. This ALU is also capable of eight-bitunsigned multiplication, which made the 6809 one of the ?rst integratedmicroprocessors with multiplication capability.
Other improvements in the 6809 included a direct page register (DPR) for amore ?exible eight- bit direct addressing mode. The 8-bit DPR, representingA[15:8], is combined with an 8-bit direct address, representing A[7:0], toform a 16-bit direct address, thereby enabling an 8-bit direct address toreference any location in the complete 64-kB address space. A 6809 alsoincluded a more advanced bus interface with direct support for an externalDMA controller. Several desktop computers, including the Tandy/RadioShack TRS-80 Color Computer, and various platforms, including arcadegames, utilized the 6809.
While still available from odd-lot retail outlets, the original 6800 family membersare no longer practical to use in many computing applications. Their capabilities,once leading edge, are now available in smaller, more integrated ICs at lowercost and with lower power consumption. However, A 6800 architecture isalive and well in the 68HC05/68HC08 and 68HC11 microcontroller familiesthat are based on the 6800/6802/6808 és 6809 architectures, respectively.These microcontrollers are available with a wide range of integrated featureswith on-board RAM, ROM (mask ROM, EE-PROM, or EPROM), serialports, timers, and analog-to-digital converters.
Other improvements in the 6809 included a direct page register (DPR) for amore ?exible eight- bit direct addressing mode. The 8-bit DPR, representingA[15:8], is combined with an 8-bit direct address, representing A[7:0], toform a 16-bit direct address, thereby enabling an 8-bit direct address toreference any location in the complete 64-kB address space. A 6809 alsoincluded a more advanced bus interface with direct support for an externalDMA controller. Several desktop computers, including the Tandy/RadioShack TRS-80 Color Computer, and various platforms, including arcadegames, utilized the 6809.
While still available from odd-lot retail outlets, the original 6800 family membersare no longer practical to use in many computing applications. Their capabilities,once leading edge, are now available in smaller, more integrated ICs at lowercost and with lower power consumption. However, A 6800 architecture isalive and well in the 68HC05/68HC08 and 68HC11 microcontroller familiesthat are based on the 6800/6802/6808 és 6809 architectures, respectively.These microcontrollers are available with a wide range of integrated featureswith on-board RAM, ROM (mask ROM, EE-PROM, or EPROM), serialports, timers, and analog-to-digital converters.
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