मार्च 10, 2010
Intel 8086 16-Bit Microprocessor Family
द्वारा पोस्ट: मरम्मत : श्रेणी: शिक्षाप्रद माइक्रोप्रोसेसरों और माइक्रो
Intel moved up to a 16-bit microprocessor, the 8086, in 1978 just two years afterintroducing the 8085 as an enhancement to the 8080. The x86 family is famousfor being chosen by IBM for their original PC. As PCs developed during thepast 20 years, the x86 family grew with the industry ?rst to 32 bits (80386,Pentium) and more recently to 64 bits (Itanium). While the 8086 was a newarchitecture, it retained certain architectural characteristics of the 8080/8085such that assembly language programs written for its predecessors could beconverted over to the 8086 with little or no modi?कटियन. This is one of thekey reasons for its initial success.
The 8086 contains various 16-bit registers as shown in Fig. 6.9, some of whichcan be manipu- lated one byte at a time. AX, BX, CX, and DX aregeneral-purpose registers that have alternate functions and that can be treatedas single 16-bit registers or as individual 8-bit registers. The accumulator,AX, and the ?ags register serve their familiar functions. BX can serve as ageneral pointer. CX is a loop iteration count register that is used inherentlyby certain instructions. DX is used as a companion register to AX whenperforming certain arithmetic operations such as integer division or handlinglong integers (32 bits).
The remaining registers are pointers of various types that index into the 8086ssomewhat awk- ward segmented memory structure. Despite being a 16-bitmicroprocessor with no register exceeding 16 bits in size, Intel recognized theneed for more than 64 kB of addressable memory in more advanced computers.One megabyte of memory space was decided upon as a suf?ciently largeaddress space in the late 1970s, but the question remained of how to accessthat memory with 16-bit pointers. Intels solution was to have programmersarbitrarily break the 1 MB address space into multiple 64-kB special-purposesegments one for instructions (code segment), two for data (primary data andextra data), and one for the stack. Memory operations must reference oneof these de?ned segments, requiring only a 16-bit pointer to address anylocation within a given segment. Segments can be located anywhere in memory,as shown in Fig. 6.10, and can be moved at will to provide ?exibility fordifferent applications. Additionally, there is no restriction on overlapping ofsegments.
Each segment register represents the upper 16 bits of a 20-bit pointer(220 = 1 MB) where the lower 4 bits are ?xed at 0. इसलिये, a segment registerdirectly points to an arbitrary location in 1 MB of memory on a 16-byte boundary.A pointer register is then added to the 20-bit segment address to yield a ?nal20-bit address, the effective address, with which to fetch or store data.Algebraically, this relationship is expressed as: effective address =(segment pointer ? 16) + offset pointer.
The 8086 contains various 16-bit registers as shown in Fig. 6.9, some of whichcan be manipu- lated one byte at a time. AX, BX, CX, and DX aregeneral-purpose registers that have alternate functions and that can be treatedas single 16-bit registers or as individual 8-bit registers. The accumulator,AX, and the ?ags register serve their familiar functions. BX can serve as ageneral pointer. CX is a loop iteration count register that is used inherentlyby certain instructions. DX is used as a companion register to AX whenperforming certain arithmetic operations such as integer division or handlinglong integers (32 bits).
The remaining registers are pointers of various types that index into the 8086ssomewhat awk- ward segmented memory structure. Despite being a 16-bitmicroprocessor with no register exceeding 16 bits in size, Intel recognized theneed for more than 64 kB of addressable memory in more advanced computers.One megabyte of memory space was decided upon as a suf?ciently largeaddress space in the late 1970s, but the question remained of how to accessthat memory with 16-bit pointers. Intels solution was to have programmersarbitrarily break the 1 MB address space into multiple 64-kB special-purposesegments one for instructions (code segment), two for data (primary data andextra data), and one for the stack. Memory operations must reference oneof these de?ned segments, requiring only a 16-bit pointer to address anylocation within a given segment. Segments can be located anywhere in memory,as shown in Fig. 6.10, and can be moved at will to provide ?exibility fordifferent applications. Additionally, there is no restriction on overlapping ofsegments.
Each segment register represents the upper 16 bits of a 20-bit pointer(220 = 1 MB) where the lower 4 bits are ?xed at 0. इसलिये, a segment registerdirectly points to an arbitrary location in 1 MB of memory on a 16-byte boundary.A pointer register is then added to the 20-bit segment address to yield a ?nal20-bit address, the effective address, with which to fetch or store data.Algebraically, this relationship is expressed as: effective address =(segment pointer ? 16) + offset pointer.
आकृति 6.9 8086 register set.
आकृति 6.10 8086 segments.
Inside the microprocessor, this math is performed by shifting the segment pointer(0×135F) left by four bits and then adding the offset pointer (0×0102) asshown below.
This segmented addressing scheme has some awkward characteristics. First,programs must orga- nize their instructions and data into 64-kB chunks andproperly keep track of which portions are be- ing accessed. If data outsideof the current segments is desired, the appropriate segment register must beupdated. Second, the same memory location can be represented by multiplecombinations of segment and offset values, which can cause confusion in sortingout which instruction is accessing which location in memory. Nonetheless,programmers and the manufacturers of their development tools have ?guredout ways to avoid these traps and others like them.
Instructions that reference memory implicitly or explicitly determine whichoffset pointer is added to which segment register to yield the desired effectiveaddress. उदाहरण के लिये, a push or pop instruction inherently uses the stackpointer in combination with the stack segment register. However, an instructionto move data from memory to the accumulator can use one of multiple pointerregisters relative to any of the segment registers.
The 8086s reset and interrupt vectors are located at opposite ends of thememory space. On reset, the instruction pointer is set to 0xFFFF0, and themicroprocessor begins executing instructions from this address. इसलिये,rather than being a true vector, the 16-byte reset region contains normalexecutable instructions. The interrupt vectors are located at the bottom ofthe memory space starting from address 0, and there are 256 vectors, onefor each of the 256 interrupt types. Each interrupt vector is composed of a2-byte segment address and a 2-byte offset address, from which a 20-biteffective address is calculated. When the 8086s INTR pin is driven high,an interrupt acknowledge process begins via the INTA* output pin. The8086 pulses INTA* low twice and, on the second pulse, the interruptingperipheral drives an interrupt type, or vector number, onto the eight lowerbits of the data bus. The vector number is used to index into the interruptvector table by multiplying it by 4 (shifting left by two bits), because each vectorconsists of four bytes. For example, interrupt type 0×03 would cause themicroprocessor to fetch four bytes from addresses 0×0C through 0×0F.Interrupts triggered by the INTR pin are all maskable via an internal control bit.Software can also trigger interrupts of various types via the INT instruction.A nonmaskable interrupt can be triggered by external hardware via the NMIpin. NMI initiates the type-2 interrupt service routine at the address indicatedby the vector at 0×08-0×0B.
Locating the reset boot code at the top of memory and the interrupt vectors atthe bottom often leads to an 8086 computer architecture with ROM at the topand some RAM at the bottom. ROM must be at the top, for obvious reasons.Placing the interrupt vector table in RAM enables a ?exible system in whichsoftware applications can install their own ISRs to perform various tasks. Onthe original IBM PC platform, it was not uncommon for programs to insert theirown ISR addresses into certain interrupt vectors located in RAM. The systemtimer and keyboard interrupts were common objects of this activity. Becausethe PCs operating system already implemented ISRs for these interrupts, theprogram could redirect the interrupt vector to its own ISR and then call thesystems default ISR when its own ISR completed execution. If properly done,this interrupt chaining process could add new features to a PC without harmingthe existing housekeeping chores performed by the standard ISRs. Chainingthe keyboard interrupt could enable a program that is normally dormant topop up each time a particular key sequence is pressed.
Despite its complexity and 16-bit processing capability, the 8086 was original lyhoused in a 40-pin DIP the same package used for most 8-bit processors of the time. Intel chose to use a multiplexed address/data scheme similar to that usedon the 8051 microcontroller, thereby saving 16 pins. The 8086s 20-bit addressbus is shared by the data bus on the lower 16 bits and by status ?ags on the upper 4 bits. Combined with additional signals, these status ?ags control the microprocessors bus interface. As with Intels other microprocessors, the 8086contains separate address spaces for memory and I/O devices. A control pinon the chip indicates whether a transaction is memory or I/O.
While the memory space is 1 MB in size, the I/O space is only 64 kB. The8086 bus interface oper- ates in one of two modes, minimum and maximum,determined by a control pin tied either high or low, respectively. In each ofthese two modes, many of the control and status pins take on different functions.In minimum mode, the control signals directly drive a standard Intel-style bussimilar to that of the 8080 और 8051, with read and write strobes and addresslatch enable. Other signals include a READY signal for inserting wait states forslow peripherals and a bus grant/acknowledge mechanism for supporting DMAor similar bus-sharing peripherals. Minimum mode is designed for smallersystems in which little address decoding logic is necessary to interface the 8086to memory and peripherals devices. Maximum mode is designed for largersystems where an Intel companion chip, the 8288 bus controller, integratesmore complex bus control logic onto an off-the-shelf IC. In maximum mode,certain status and control pins communicate more information about what typeof transaction is being performed at any given time, enabling the 8288 to takeappropriate action.
The 8086s 16-bit data bus is capable of transacting a single byte at a time forpurposes of access- ing byte-wide peripherals. One early advantage of the 8086was its backward bus compatibility with the 8080/8085. In the 1970s, Intelmanufactured a variety of I/O peripherals such as timers and parallel I/Odevices for their eight-bit microprocessors. The 8086s ability to performbyte-wide trans- actions enabled easy reuse of existing eight-bit peripheralproducts. Two signals, byte high enable (BHE*) and address bit zero (एक[0]),communicate the width and active byte of each bus transaction as shown inTable 6.3.
Instructions that reference memory implicitly or explicitly determine whichoffset pointer is added to which segment register to yield the desired effectiveaddress. उदाहरण के लिये, a push or pop instruction inherently uses the stackpointer in combination with the stack segment register. However, an instructionto move data from memory to the accumulator can use one of multiple pointerregisters relative to any of the segment registers.
The 8086s reset and interrupt vectors are located at opposite ends of thememory space. On reset, the instruction pointer is set to 0xFFFF0, and themicroprocessor begins executing instructions from this address. इसलिये,rather than being a true vector, the 16-byte reset region contains normalexecutable instructions. The interrupt vectors are located at the bottom ofthe memory space starting from address 0, and there are 256 vectors, onefor each of the 256 interrupt types. Each interrupt vector is composed of a2-byte segment address and a 2-byte offset address, from which a 20-biteffective address is calculated. When the 8086s INTR pin is driven high,an interrupt acknowledge process begins via the INTA* output pin. The8086 pulses INTA* low twice and, on the second pulse, the interruptingperipheral drives an interrupt type, or vector number, onto the eight lowerbits of the data bus. The vector number is used to index into the interruptvector table by multiplying it by 4 (shifting left by two bits), because each vectorconsists of four bytes. For example, interrupt type 0×03 would cause themicroprocessor to fetch four bytes from addresses 0×0C through 0×0F.Interrupts triggered by the INTR pin are all maskable via an internal control bit.Software can also trigger interrupts of various types via the INT instruction.A nonmaskable interrupt can be triggered by external hardware via the NMIpin. NMI initiates the type-2 interrupt service routine at the address indicatedby the vector at 0×08-0×0B.
Locating the reset boot code at the top of memory and the interrupt vectors atthe bottom often leads to an 8086 computer architecture with ROM at the topand some RAM at the bottom. ROM must be at the top, for obvious reasons.Placing the interrupt vector table in RAM enables a ?exible system in whichsoftware applications can install their own ISRs to perform various tasks. Onthe original IBM PC platform, it was not uncommon for programs to insert theirown ISR addresses into certain interrupt vectors located in RAM. The systemtimer and keyboard interrupts were common objects of this activity. Becausethe PCs operating system already implemented ISRs for these interrupts, theprogram could redirect the interrupt vector to its own ISR and then call thesystems default ISR when its own ISR completed execution. If properly done,this interrupt chaining process could add new features to a PC without harmingthe existing housekeeping chores performed by the standard ISRs. Chainingthe keyboard interrupt could enable a program that is normally dormant topop up each time a particular key sequence is pressed.
Despite its complexity and 16-bit processing capability, the 8086 was original lyhoused in a 40-pin DIP the same package used for most 8-bit processors of the time. Intel chose to use a multiplexed address/data scheme similar to that usedon the 8051 microcontroller, thereby saving 16 pins. The 8086s 20-bit addressbus is shared by the data bus on the lower 16 bits and by status ?ags on the upper 4 bits. Combined with additional signals, these status ?ags control the microprocessors bus interface. As with Intels other microprocessors, the 8086contains separate address spaces for memory and I/O devices. A control pinon the chip indicates whether a transaction is memory or I/O.
While the memory space is 1 MB in size, the I/O space is only 64 kB. The8086 bus interface oper- ates in one of two modes, minimum and maximum,determined by a control pin tied either high or low, respectively. In each ofthese two modes, many of the control and status pins take on different functions.In minimum mode, the control signals directly drive a standard Intel-style bussimilar to that of the 8080 और 8051, with read and write strobes and addresslatch enable. Other signals include a READY signal for inserting wait states forslow peripherals and a bus grant/acknowledge mechanism for supporting DMAor similar bus-sharing peripherals. Minimum mode is designed for smallersystems in which little address decoding logic is necessary to interface the 8086to memory and peripherals devices. Maximum mode is designed for largersystems where an Intel companion chip, the 8288 bus controller, integratesmore complex bus control logic onto an off-the-shelf IC. In maximum mode,certain status and control pins communicate more information about what typeof transaction is being performed at any given time, enabling the 8288 to takeappropriate action.
The 8086s 16-bit data bus is capable of transacting a single byte at a time forpurposes of access- ing byte-wide peripherals. One early advantage of the 8086was its backward bus compatibility with the 8080/8085. In the 1970s, Intelmanufactured a variety of I/O peripherals such as timers and parallel I/Odevices for their eight-bit microprocessors. The 8086s ability to performbyte-wide trans- actions enabled easy reuse of existing eight-bit peripheralproducts. Two signals, byte high enable (BHE*) and address bit zero (एक[0]),communicate the width and active byte of each bus transaction as shown inTable 6.3.
Intels microprocessors follow the little-endian byte ordering convention.Little-endian refers to the practice of locating the LSB of a multibyte quantity ina lower address and the MSB in a higher address. In a little-endian 16-bitmicroprocessor, the value 0×1234 would be stored in memory by locating 0×12into address 1 and 0×34 into address 0. Big-endian is the opposite: locating theLSB in the higher address and the MSB in the lower address. इसलिये, abig-endian 16-bit microprocessor would store 0×12 into address 0 and 0×34into address 1. To clarify the difference, Table 6.4 shows little-endian versusbig-endian for 16- and 32-bit quantities as viewed from a memory chipsperspective. यहां, ADDR represents the base address of a multibyte dataelement.
Proponents of little-endian argue that it makes better sense, because the lowbyte goes into the low address. Proponents of big-endian argue that it makes better sense, because data is stored in memory as you would read and interpret it. Thechoice of endianness is rather religious and comes down to personal preference.Of course, if you are designing with a little-endian microprocessor, life will bemade simpler to maintain the endianness consistently throughout the system.
Proponents of little-endian argue that it makes better sense, because the lowbyte goes into the low address. Proponents of big-endian argue that it makes better sense, because data is stored in memory as you would read and interpret it. Thechoice of endianness is rather religious and comes down to personal preference.Of course, if you are designing with a little-endian microprocessor, life will bemade simpler to maintain the endianness consistently throughout the system.
At the time of the 8086s introduction, 16-bit desktop computer systems werealmost unheard of and could be substantially more expensive than 8-bit systemsas a result of the increased memory size required to support the larger bus. Toalleviate this problem and speed market acceptance of its architecture, Intelintroduced the 8088 microprocessor in 1979, which was essentially an 8086with an eight-bit data bus. A lower-cost computer system could be built with the8088, because fewer EPROM and RAM chips were necessary, system logicdid not have to deal with two bytes at a time, and less circuit board wiring wasrequired. A tremendous bene?t to Intel in designing the 8088 was the factthat it was chosen by IBM as the low-cost 16-bit heart of the original PC/XTdesktop computer, thereby locking the x86 microprocessor family into theIBM PC architecture for decades to come.
A variety of companion chips were developed by Intel to supplement the8086/8088. Among these was the 8087 math coprocessor that enhanced the 8086scomputational capabilities with ?oating-point arithmetic operations. Floating-pointarithmetic refers to a computers handling of real numbers as compared to integers.The task of adding or multiplying two real numbers of arbitrary magnitude is farmore complex than similar integer operations. Certain applications such as scienti?csimulations and realistic games that construct a virtual reality world make signi?cantuse of ?oating-point operations. The 8087 is a coprocessor rather than a peripheral,because it sits on the microprocessor bus in parallel with the 8086 and watches forspecial ?oating-point instructions.
These instructions are then executed automatically by the 8087 rather than havingto wait for the 8086 to request an operation. The 8086 was designed with the 8087sexistence in mind and ignores instructions destined for the 8087. इसलिये, softwaremust speci?cally know if a math coprocessor is installed to run correctly. Manyprograms that ran on older systems with or without a coprocessor would ?rst testto see if the coprocessor was installed and then execute either an optimized set ofroutines for the 8087 or a slower set of routines that emulated the ?oating-pointoperations via conventional 8086 instructions.
As the x86 family developed, the optional math coprocessor was eventuallyintegrated alongside the integer processor on the same silicon chip. The 8087 gaveway to the 80287 और 80387 when the 80286 और 80386 microprocessors wereproduced. When Intel introduced the 80486, the coprocessor, या ?oating-pointunit (FPU), was integrated on chip. This integration resulted in a somewhat moreexpensive product, so Intel released a lower-cost 80486SX microprocessorwithout the coprocessor. An 80487SX was made available to upgrade systemsoriginally sold with the 80486SX chips, but the overall situation provedsomewhat chaotic with various permutations of microprocessors and systemswith and without coprocessors. Starting with the Pentium, all of Intels high-endmicroprocessors contain integrated FPUs. This trend is not unique to Intel.High-performance microprocessors in general began integrating the FPU atroughly the same time because of the performance bene?ts and the overallsimplicity of placing the microprocessor and FPU onto the same chip.
A variety of companion chips were developed by Intel to supplement the8086/8088. Among these was the 8087 math coprocessor that enhanced the 8086scomputational capabilities with ?oating-point arithmetic operations. Floating-pointarithmetic refers to a computers handling of real numbers as compared to integers.The task of adding or multiplying two real numbers of arbitrary magnitude is farmore complex than similar integer operations. Certain applications such as scienti?csimulations and realistic games that construct a virtual reality world make signi?cantuse of ?oating-point operations. The 8087 is a coprocessor rather than a peripheral,because it sits on the microprocessor bus in parallel with the 8086 and watches forspecial ?oating-point instructions.
These instructions are then executed automatically by the 8087 rather than havingto wait for the 8086 to request an operation. The 8086 was designed with the 8087sexistence in mind and ignores instructions destined for the 8087. इसलिये, softwaremust speci?cally know if a math coprocessor is installed to run correctly. Manyprograms that ran on older systems with or without a coprocessor would ?rst testto see if the coprocessor was installed and then execute either an optimized set ofroutines for the 8087 or a slower set of routines that emulated the ?oating-pointoperations via conventional 8086 instructions.
As the x86 family developed, the optional math coprocessor was eventuallyintegrated alongside the integer processor on the same silicon chip. The 8087 gaveway to the 80287 और 80387 when the 80286 और 80386 microprocessors wereproduced. When Intel introduced the 80486, the coprocessor, या ?oating-pointunit (FPU), was integrated on chip. This integration resulted in a somewhat moreexpensive product, so Intel released a lower-cost 80486SX microprocessorwithout the coprocessor. An 80487SX was made available to upgrade systemsoriginally sold with the 80486SX chips, but the overall situation provedsomewhat chaotic with various permutations of microprocessors and systemswith and without coprocessors. Starting with the Pentium, all of Intels high-endmicroprocessors contain integrated FPUs. This trend is not unique to Intel.High-performance microprocessors in general began integrating the FPU atroughly the same time because of the performance bene?ts and the overallsimplicity of placing the microprocessor and FPU onto the same chip.
द्वारा : E-पुस्तक Complete_Digital_Design
