Different external serial modems use an assortment of different types of cables. Make sure the cable is actually a modem cable; other cables might fit, but that doesn’t mean they’ll work. Also try testing the cable in a cable tester. With USB cables, it is often easy to swap with a known good cable.

For information on troubleshooting network connections, see “Troubleshooting Internet Connections.”

Motorola followed its 6800 family by leaping directly to a hybrid 16/32-bit
microprocessor architecture. Introduced in 1979, the 68000 is a 16-bit
microprocessor, due to its 16-bit ALU, but it contains all 32-bit registers and
a linear, nonsegmented 32-bit address space. (The original 68000 did not
bring out all 32 address bits as signal pins but, more importantly, there are no
architectural limitations of using all 32 bits.) That the register and memory
architecture is inherently 32 bits made the 68000 family easily scalable to
a full 32-bit internal architecture. Motorola upgraded the 68000 family with
true 32-bit devices, including the 68020, 68040, and 68060, until switching
to the PowerPC architecture in the latter portion of the 1990s for new
high-performance computing applications. Apple Computer used the 68000
family in their popular line of Macintosh desktop computers. Today, the
68000 family lives on primarily as a mid-level embedded-processor core
product. Motorola manufacturers a variety of high-end microcontrollers
that use 32-bit 68000 microprocessor cores. However, in recent years
Motorola has begun migrating these products, as well as their general-purpose
microprocessors, to the PowerPC architecture, reducing the number of new
designs that use the 68000 family.

The 68000 inherently supports modern software operating systems (OSs)
by recognizing two modes of operation: supervisor mode and user mode.
A modern OS does not grant unlimited access to application software in
using the computers resources. Rather, the OS establishes a restricted
operating environment into which a program is loaded. Depending on the
speci?c OS, applications may not be able to access certain areas of memory
or I/O devices that have been declared off limits by the OS. This can prevent
a fault in one program from crashing the entire computer system. The OS
kernel, the core low-level software that keeps the computer running properly,
has special privi- leges that allow it unrestricted access to the computer for
the purposes of establishing all of the rules and boundaries under which
programs run. Hardware support for multiple privilege levels is crucial for
such a scheme to prevent unauthorized programs from freely accessing restricted
resources. As microprocessors developed over the last few decades, more
hardware support for OS privileges was added. That the 68000 included such
concepts in 1979 is a testimony to its scalable architecture.

Sixteen 32-bit general-purpose registers, one of which is a user stack pointer
(USP), and an 8-bit condition code register are accessible from user mode as
shown in Fig. 6.11. Additionally, a supervisor stack pointer (SSP) and eight
additional status bits are accessible from supervisor mode. Computer systems
do not have to implement the two modes of operation if the application does
not require it. In such cases, the 68000 can be run permanently in supervisor
mode to enable full access to all resources by all programs. The SSP is used
for stack operations while in supervisor mode, and the USP is used for stack
operations in user mode. User mode programs cannot change the USP,
preventing them from relocating their stacks. Most modern operating systems
are multitasking, mean- ing that they run multiple programs simultaneously. In
reality, a microprocessor can only run one program at a time. A multitasking
OS uses a timer to periodically interrupt the microprocessor, perhaps 20 to
100 times per second, and place it into supervisor mode. Each time supervisor
mode is invoked, the kernel performs various maintenance tasks and swaps
the currently running program with the next program in the list of running programs.
This swap, or context switch, can entail substantial modi?cations to the
microprocessors state when it returns from the kernel timer interrupt. In the
case of an original 68000 microprocessor, the kernel could change the return
value of the PC, USP, the 16 general-purpose registers, and the status register.
When normal execution resumes, the microprocessor is now executing a
different program in exactly the same state at which it was previously interrupted,
because all of its registers are in the same state in which they were left. In such a
scenario, each program has its own private stack, pointed to by a
kernel-designated stack pointer.

The eight data registers, D0D7, can be used for arbitrary ALU operations. The
eight address registers, A0A7, can all be used as base addresses for indirect
addressing and for certain 16- and 32-bit ALU operations. All 16 registers can
be used as index registers. While operating in user mode, it is illegal to access
the SSP or the supervisor portion of the status register, SR. Such instructions will
cause an exception, whereby a particular interrupt is asserted, which causes the
68000 to enter supervisor mode to handle the fault. (Exception and interrupt are
often used synonymously in computer contexts.) Very often, the OS kernel will
terminate an application that causes an exception to be generated. The registers
shown above are present in all 68000 family members and, as such, are
software is compatible with subsequent 68xxx microprocessors. Newer
microprocessors contain additional registers that provide more advanced privilege
levels and memory management. While the 68000 architecture fundamentally
supports a 4-GB (32-bit) address space, early devices were limited in terms
of how much physical memory could actually be addressed as a result of pin
limitations in the packaging. The original 68000 was housed in a 64-pin DIP,
leaving only 24 address bits usable, for a total usable memory space of 16 MB.
When Motorola introduced the 68020, the ?rst fully 32-bit 68000 microprocessor,
all 32 address bits were made available. The 68000 devices are big-endian,
so the MSB is stored in the lowest address of a multibyte word.

FIGURE 6.11 68000 register set.

The 68000 supports a 16-MB address space, but only 23 address bits, A[23:1],
are actually brought out of the chip as signal pins. A[0] is omitted and is unnecessary,
because it would specify whether an even (A[0] = 0) or odd (A[0] = 1) byte is
being accessed; and, because the bus is 16 bits wide, both even and odd bytes
can be accessed simultaneously. However, provisions are made for byte-wide
accesses in situations where the 68000 is connected to legacy eight-bit peripherals
or memories. Two data strobes, upper (UDS*) and lower (LDS*), indicate
which bytes are being ac- cessed during any given bus cycle. These strobes are
generated by the 68000 according to the state of the internal A0 bit and
information on the size of the requested transaction. Bus transactions are
triggered by the assertion of address strobe (AS*), the appropriate data strobes,
and R/W* as shown in Fig. 6.12. Prior to AS*, the 68000 asserts the desired
address and a three-bit function code bus, FC[2:0]. The function code bus
indicates which mode the processor is in and whether the transaction is a
program or data access. This information can be used by external logic to
qualify transactions to certain sensitive memory spaces that may be off limits
to user programs. When read data is ready, the external bus interface logic
asserts data transfer acknowledge (DTACK*) to inform the microprocessor
that the transaction is complete. As shown, the 68000 bus can be operated in
a fully asyn-chronous manner. When operated asynchronously, DTACK* is
removed after the strobes are removed, ensuring that the 68000 detected the
assertion of DTACK*. If DTACK* is removed prior to the strobes, there
is a chance of marginal timing where the 68000 may not properly detect the
acknowledge, and it may wait forever for an acknowledge that has now
passed. Writes are very similar to reads, with the obvious difference that
R/W* is brought low, and data is driven by the 68000. Another difference
is that the data strobe assertion lags that of AS*.

FIGURE 6.12 68000 asynchronous bus timing.

Advanced microprocessors such as the 68000 are designed to recognize fault
conditions wherein the requested bus transaction cannot be completed. A bus
fault can be caused by a variety of problems, including unauthorized access
(e.g., user mode tries to write to a protected supervisor data space) or an
access to a section of memory that is not ?lled by a memory or peripheral
device. Software should never access areas of memory that are off limits,
because the results are unpredictable. Therefore, rather than simply issuing
a false DTACK* and continuing with normal operation, the 68000 contains
a bus error signal (BERR*) that behaves like DTACK* but triggers an
exception rather than continuing normal execution. It is the responsibility of
external logic to manage the DTACK* and BERR* signals according to
the speci?c con?guration and requirements of the particular system.

Operating the 68000 bus in an asynchronous manner is easy, but it reduces
its bandwidth, because delays must be built into the acknowledge process to
guarantee that both the 68000 and the interface logic maintain synchronization.
Figure 6.12 shows read data being asserted prior to DTACK* and an
arbitrary delay between the release of AS* and that of DTACK*. The data
delay is necessary to guar- antee that the 68000 will see valid data when it
detects a valid acknowledge. The second delay is necessary to ensure that
the 68000 completes the transaction, as noted previously. These delays can
be eliminated if the bus is operated synchronously by distributing the
microprocessor clock to the interface logic and guaranteeing that various
setup and hold timing requirements are met as speci?ed by Motorola. In
such a con?guration, it is known from Motorolas data sheet that the
68000 looks for DTACK* each clock cycle, starting at a ?xed time after
asserting the strobes, and then samples the read-data one cycle after detecting
DTACK* being active. Because synchronous timing rules are obeyed,
it is guaranteed that the 68000 properly detects DTACK* and, therefore,
DTACK* can be removed without having to wait for the removal of the
strobes. 68000 synchronous bus timing is shown in Fig. 6.13, where each
transaction lasts a minimum of four clock cycles. A four-cycle transaction
is a zero wait state access. Wait states can be added by simply delaying
the assertion of DTACK* to the next cycle. However, to maintain proper
timing, DTACK* (and BERR* and read-data) must always obey proper
setup and hold requirements. As shown in the timing diagram, each
signal transition, or edge, is time-bounded relative to a clock edge.

Read timing allows a single clock cycle between data strobe assertion and the
return of DTACK* for a zero wait-state transaction. However, zero wait-state
writes require DTACK* assertion at roughly the same time as the data strobes.
Therefore, the bus interface logic must make its decision on asserting DTACK*
based on the requested address when AS* is asserted. If the requested device
is operational, DTACK* can be immediately asserted for a fast transaction.
Unlike reads, where the microprocessor must wait for a device to return data,
writes can be acknowledged before they are actually transferred to the device.
In such a scheme, writes are posted within the bus interface logic.

One or two cycles later, when the device accepts the posted write data, the
bus interface logic ?nally completes the transaction without having delayed
the microprocessor. If completion of the posted- write transaction takes
longer than a few cycles, it could force a subsequent access to the same
device to incur wait states. Either a read or a write would be blocked
until the original write was able to complete, thus freeing the device to
handle the next transaction.

FIGURE 6.13 68000 synchronous bus timing.

In addition to the basic bus interface, the 68000 supports bus arbitration to
enable DMA or other logic to use the microprocessor bus for arbitrary applications.
A bus request (BR*) signal is asserted by a device that wants to temporarily gain
control of the bus. On the next clock cycle, when the microprocessor is not
inhibited by other operations, it asserts a bus grant (BG*) signal and places its
address, data, and control signals into tri-state so that they may be driven by the
other device. The re- questing device then asserts bus grant acknowledge
(BGACK*) to signal that it is controlling the bus, and it is then free to assert
its own strobes, address, and data signals.

A variety of interrupts and exceptions are supported by the 68000. Some are
triggered as a result of instruction execution and some by external signals (e.g.,
BERR* or an interrupt request). Examples of instruction exceptions are illegal
user mode register accesses or a divide-by-zero error. Most microprocessors
that provide division capability contain some type of divide-by-zero error
handling, because the result of such an operation is mathematically unde?ned
and is usually the result of a fault in the program. The 68000 contains an
exception vector table that is 1,024 bytes long and resides at the beginning
of memory at address 0. In a multitasking system, the bus interface logic may
restrict access to the vector table to supervisor mode only. In such a case, a
bus error could be triggered if a user mode program, indicated by FC[2:0],
tried to write the table. Each of the 256 vector entries is four bytes long
and provides the starting address of the associated ISR. The one deviation
from this rule is the reset vector, which actually consists of two entries at word
addresses 0 and 4.

Upon reset, the 68000 fetches an initial PC value from address 4 and an initial
SSP value from address 0. Vectors 0 through 63 are assigned or reserved by
Motorola for various hardware exceptions. Vectors 64 through 255 are
assigned as user interrupt vectors. Like other microprocessors in its category,
the 68000 supports bus vectoring of user interrupts where an external interrupt
controller asserts an interrupt number onto the data bus during an interrupt
acknowledge cycle performed by the 68000 in response to an interrupt
request. This interrupt number is multiplied by four and used to index into
the exception table to fetch the address of the appropriate ISR.

By : E-book Complete_Digital_Design

Intel moved up to a 16-bit microprocessor, the 8086, in 1978 just two years after
introducing the 8085 as an enhancement to the 8080. The x86 family is famous
for being chosen by IBM for their original PC. As PCs developed during the
past 20 years, the x86 family grew with the industry ?rst to 32 bits (80386,
Pentium) and more recently to 64 bits (Itanium). While the 8086 was a new
architecture, it retained certain architectural characteristics of the 8080/8085
such that assembly language programs written for its predecessors could be
converted over to the 8086 with little or no modi?cation. This is one of the
key reasons for its initial success.

The 8086 contains various 16-bit registers as shown in Fig. 6.9, some of which
can be manipu- lated one byte at a time. AX, BX, CX, and DX are
general-purpose registers that have alternate functions and that can be treated
as single 16-bit registers or as individual 8-bit registers. The accumulator,
AX, and the ?ags register serve their familiar functions. BX can serve as a
general pointer. CX is a loop iteration count register that is used inherently
by certain instructions. DX is used as a companion register to AX when
performing certain arithmetic operations such as integer division or handling
long integers (32 bits).

The remaining registers are pointers of various types that index into the 8086s
somewhat awk- ward segmented memory structure. Despite being a 16-bit
microprocessor with no register exceeding 16 bits in size, Intel recognized the
need for more than 64 kB of addressable memory in more advanced computers.
One megabyte of memory space was decided upon as a suf?ciently large
address space in the late 1970s, but the question remained of how to access
that memory with 16-bit pointers. Intels solution was to have programmers
arbitrarily break the 1 MB address space into multiple 64-kB special-purpose
segments one for instructions (code segment), two for data (primary data and
extra data), and one for the stack. Memory operations must reference one
of these de?ned segments, requiring only a 16-bit pointer to address any
location within a given segment. Segments can be located anywhere in memory,
as shown in Fig. 6.10, and can be moved at will to provide ?exibility for
different applications. Additionally, there is no restriction on overlapping of
segments.

Each segment register represents the upper 16 bits of a 20-bit pointer
(2²⁰ = 1 MB) where the lower 4 bits are ?xed at 0. Therefore, a segment register
directly points to an arbitrary location in 1 MB of memory on a 16-byte boundary.
A pointer register is then added to the 20-bit segment address to yield a ?nal
20-bit address, the effective address, with which to fetch or store data.
Algebraically, this relationship is expressed as: effective address =
(segment pointer ? 16) + offset pointer.

FIGURE 6.9 8086 register set.

FIGURE 6.10 8086 segments.

Inside the microprocessor, this math is performed by shifting the segment pointer
(0×135F) left by four bits and then adding the offset pointer (0×0102) as
shown below.

This segmented addressing scheme has some awkward characteristics. First,
programs must orga- nize their instructions and data into 64-kB chunks and
properly keep track of which portions are be- ing accessed. If data outside
of the current segments is desired, the appropriate segment register must be
updated. Second, the same memory location can be represented by multiple
combinations of segment and offset values, which can cause confusion in sorting
out which instruction is accessing which location in memory. Nonetheless,
programmers and the manufacturers of their development tools have ?gured
out ways to avoid these traps and others like them.

Instructions that reference memory implicitly or explicitly determine which
offset pointer is added to which segment register to yield the desired effective
address. For example, a push or pop instruction inherently uses the stack
pointer in combination with the stack segment register. However, an instruction
to move data from memory to the accumulator can use one of multiple pointer
registers relative to any of the segment registers.

The 8086s reset and interrupt vectors are located at opposite ends of the
memory space. On reset, the instruction pointer is set to 0xFFFF0, and the
microprocessor begins executing instructions from this address. Therefore,
rather than being a true vector, the 16-byte reset region contains normal
executable instructions. The interrupt vectors are located at the bottom of
the memory space starting from address 0, and there are 256 vectors, one
for each of the 256 interrupt types. Each interrupt vector is composed of a
2-byte segment address and a 2-byte offset address, from which a 20-bit
effective address is calculated. When the 8086s INTR pin is driven high,
an interrupt acknowledge process begins via the INTA* output pin. The
8086 pulses INTA* low twice and, on the second pulse, the interrupting
peripheral drives an interrupt type, or vector number, onto the eight lower
bits of the data bus. The vector number is used to index into the interrupt
vector table by multiplying it by 4 (shifting left by two bits), because each vector
consists of four bytes. For example, interrupt type 0×03 would cause the
microprocessor to fetch four bytes from addresses 0×0C through 0×0F.
Interrupts triggered by the INTR pin are all maskable via an internal control bit.
Software can also trigger interrupts of various types via the INT instruction.
A nonmaskable interrupt can be triggered by external hardware via the NMI
pin. NMI initiates the type-2 interrupt service routine at the address indicated
by the vector at 0×08-0×0B.

Locating the reset boot code at the top of memory and the interrupt vectors at
the bottom often leads to an 8086 computer architecture with ROM at the top
and some RAM at the bottom. ROM must be at the top, for obvious reasons.
Placing the interrupt vector table in RAM enables a ?exible system in which
software applications can install their own ISRs to perform various tasks. On
the original IBM PC platform, it was not uncommon for programs to insert their
own ISR addresses into certain interrupt vectors located in RAM. The system
timer and keyboard interrupts were common objects of this activity. Because
the PCs operating system already implemented ISRs for these interrupts, the
program could redirect the interrupt vector to its own ISR and then call the
systems default ISR when its own ISR completed execution. If properly done,
this interrupt chaining process could add new features to a PC without harming
the existing housekeeping chores performed by the standard ISRs. Chaining
the keyboard interrupt could enable a program that is normally dormant to
pop up each time a particular key sequence is pressed.

Despite its complexity and 16-bit processing capability, the 8086 was originally
housed in a 40-pin DIP the same package used for most 8-bit processors of the
time. Intel chose to use a multiplexed address/data scheme similar to that used
on the 8051 microcontroller, thereby saving 16 pins. The 8086s 20-bit address
bus is shared by the data bus on the lower 16 bits and by status ?ags on the
upper 4 bits. Combined with additional signals, these status ?ags control the
microprocessors bus interface. As with Intels other microprocessors, the 8086
contains separate address spaces for memory and I/O devices. A control pin
on the chip indicates whether a transaction is memory or I/O.

While the memory space is 1 MB in size, the I/O space is only 64 kB. The
8086 bus interface oper- ates in one of two modes, minimum and maximum,
determined by a control pin tied either high or low, respectively. In each of
these two modes, many of the control and status pins take on different functions.
In minimum mode, the control signals directly drive a standard Intel-style bus
similar to that of the 8080 and 8051, with read and write strobes and address
latch enable. Other signals include a READY signal for inserting wait states for
slow peripherals and a bus grant/acknowledge mechanism for supporting DMA
or similar bus-sharing peripherals. Minimum mode is designed for smaller
systems in which little address decoding logic is necessary to interface the 8086
to memory and peripherals devices. Maximum mode is designed for larger
systems where an Intel companion chip, the 8288 bus controller, integrates
more complex bus control logic onto an off-the-shelf IC. In maximum mode,
certain status and control pins communicate more information about what type
of transaction is being performed at any given time, enabling the 8288 to take
appropriate action.

The 8086s 16-bit data bus is capable of transacting a single byte at a time for
purposes of access- ing byte-wide peripherals. One early advantage of the 8086
was its backward bus compatibility with the 8080/8085. In the 1970s, Intel
manufactured a variety of I/O peripherals such as timers and parallel I/O
devices for their eight-bit microprocessors. The 8086s ability to perform
byte-wide trans- actions enabled easy reuse of existing eight-bit peripheral
products. Two signals, byte high enable (BHE*) and address bit zero (A[0]),
communicate the width and active byte of each bus transaction as shown in
Table 6.3.

Intels microprocessors follow the little-endian byte ordering convention.
Little-endian refers to the practice of locating the LSB of a multibyte quantity in
a lower address and the MSB in a higher address. In a little-endian 16-bit
microprocessor, the value 0×1234 would be stored in memory by locating 0×12
into address 1 and 0×34 into address 0. Big-endian is the opposite: locating the
LSB in the higher address and the MSB in the lower address. Therefore, a
big-endian 16-bit microprocessor would store 0×12 into address 0 and 0×34
into address 1. To clarify the difference, Table 6.4 shows little-endian versus
big-endian for 16- and 32-bit quantities as viewed from a memory chips
perspective. Here, ADDR represents the base address of a multibyte data
element.

Proponents of little-endian argue that it makes better sense, because the low
byte goes into the low address. Proponents of big-endian argue that it makes better
sense, because data is stored in memory as you would read and interpret it. The
choice of endianness is rather religious and comes down to personal preference.
Of course, if you are designing with a little-endian microprocessor, life will be
made simpler to maintain the endianness consistently throughout the system.

At the time of the 8086s introduction, 16-bit desktop computer systems were
almost unheard of and could be substantially more expensive than 8-bit systems
as a result of the increased memory size required to support the larger bus. To
alleviate this problem and speed market acceptance of its architecture, Intel
introduced the 8088 microprocessor in 1979, which was essentially an 8086
with an eight-bit data bus. A lower-cost computer system could be built with the
8088, because fewer EPROM and RAM chips were necessary, system logic
did not have to deal with two bytes at a time, and less circuit board wiring was
required. A tremendous bene?t to Intel in designing the 8088 was the fact
that it was chosen by IBM as the low-cost 16-bit heart of the original PC/XT
desktop computer, thereby locking the x86 microprocessor family into the
IBM PC architecture for decades to come.

A variety of companion chips were developed by Intel to supplement the
8086/8088. Among these was the 8087 math coprocessor that enhanced the 8086s
computational capabilities with ?oating-point arithmetic operations. Floating-point
arithmetic refers to a computers handling of real numbers as compared to integers.
The task of adding or multiplying two real numbers of arbitrary magnitude is far
more complex than similar integer operations. Certain applications such as scienti?c
simulations and realistic games that construct a virtual reality world make signi?cant
use of ?oating-point operations. The 8087 is a coprocessor rather than a peripheral,
because it sits on the microprocessor bus in parallel with the 8086 and watches for
special ?oating-point instructions.

These instructions are then executed automatically by the 8087 rather than having
to wait for the 8086 to request an operation. The 8086 was designed with the 8087s
existence in mind and ignores instructions destined for the 8087. Therefore, software
must speci?cally know if a math coprocessor is installed to run correctly. Many
programs that ran on older systems with or without a coprocessor would ?rst test
to see if the coprocessor was installed and then execute either an optimized set of
routines for the 8087 or a slower set of routines that emulated the ?oating-point
operations via conventional 8086 instructions.

As the x86 family developed, the optional math coprocessor was eventually
integrated alongside the integer processor on the same silicon chip. The 8087 gave
way to the 80287 and 80387 when the 80286 and 80386 microprocessors were
produced. When Intel introduced the 80486, the coprocessor, or ?oating-point
unit (FPU), was integrated on chip. This integration resulted in a somewhat more
expensive product, so Intel released a lower-cost 80486SX microprocessor
without the coprocessor. An 80487SX was made available to upgrade systems
originally sold with the 80486SX chips, but the overall situation proved
somewhat chaotic with various permutations of microprocessors and systems
with and without coprocessors. Starting with the Pentium, all of Intels high-end
microprocessors contain integrated FPUs. This trend is not unique to Intel.
High-performance microprocessors in general began integrating the FPU at
roughly the same time because of the performance bene?ts and the overall
simplicity of placing the microprocessor and FPU onto the same chip.

By : E-book Complete_Digital_Design

Modems can be troublesome. If you have a telephone communications problem, there are a number of things you can do to check to see if the modem is working.

Here is a list of places in Windows where you can check to see whether a modem is working:

1. 
   

   Modem Properties in Device Manager, General page: If you see a message that indicates a problem, the modem might need to be reinstalled or replaced. Follow the directions or from the modem manufacturer to reinstall the driver.

   
   
2. 
   

   Query Modem: Go to Modem Properties from either Control Panel or Device Manager and click the Diagnostics tab if one is present. Then, click the Query Modem button and wait for the report. If the last couple entries in the report indicate OK, the query hasn’t detected a problem. You will often see the line “COMMAND NOT SUPPORTED” at one point in the report. You can ignore this.

   
   
3. 
   

   HyperTerminal: Go to Start > Programs (or All Programs) > Accessories > Communications > HyperTerminal, if it is installed. You will be prompted to set up a connection. Give it a simple name; you won’t be saving it. Figure 8.9 shows this page.

   
   

   
   Figure 8.9: Naming a HyperTerminal connection.

Then, enter a single-digit telephone number. Make sure your modem is listed in the Connect using box. Click OK and you will be prompted to dial the number you entered. Click Cancel. You will see a blank HyperTerminal window. Type “AT” and then press . A working modem should respond with “OK,” as shown in Figure 8.10. Then, you can close HyperTerminal and elect not to save the connection.

Figure 8.10: Autodetecting the modem in HyperTerminal.

It is also a good idea to test a suspect modem with every function in which it can be used on the computer. This is to rule out the possibility that a program, rather than the modem, is malfunctioning. For example, if a modem works with faxing and Phone Dialer (Start > Programs (or All Programs) > Accessories > Communications > Phone Dialer), but not on the Internet, it is likely that the problem is in the Internet software or service rather than with the hardware.

It is unfortunately common to get certain numbered error messages such as 619 or 693 when trying to connect using a modem. You might try several times in a row and get several different error messages. Often, these error messages bear no relationship to the truth. When you get one of these, first attempt to rule out the problem that the message indicates, assuming you can understand the message. The problem could be as simple as a bad telephone cord, the Caps Lock being on and altering the password, or that the telephone line is in use. Other possibilities include problems with the remote computer or service, or incorrect password or username. If the computer locks up every time you try to connect, you probably have a resource conflict. See Chapter 2 for information on resolving it.

Once you have ruled these out, the next step is to reboot the computer, especially if you have a laptop. With some laptops, a design flaw causes certain functions not to work after the computer comes out of standby or hibernation. Rebooting might solve other problems as well. If none of these steps works, delete the connection and recreate it. If you still have the problem, it is time to try new hardware. Swap the modem for a known good unit and retry the connection. This is the perfect time to try an external modem if you have one. If you still can’t connect, and the modem is removable, try it in another system.

If a built-in modem on a laptop fails and you have reinstalled the driver to no avail, unless the laptop is under warranty, your only recourses are to install a PC-Card modem or use an external serial or USB modem. You might want to disable the built-in modem in the BIOS, if such a setting exists. Note, however, that sometimes seemingly permanent modem failures can occasionally resolve themselves over time.

By : Book-PC Repair and Maintenance: A Practical Guide

Computer architecture is central to the design of digital systems, because most
digital systems are, at their core, computers surrounded by varying mixes of
interfaces to the outside world. It is dif?cult to know at the outset of a project how
advanced architectural concepts may ?gure into a design, because advanced
does not necessarily mean expensive or complex. Many technologies that were
originally developed for high-end supercomputers and mainframes eventually
found their way into consumer electronics and other less-expensive digital systems.
This is why a digital engineer bene- ?ts from a broad understanding of advanced
microprocessor and computing concepts a wider palette of potential solutions
enables a more creative and effective design process.

This chapter introduces a wide range of technologies that are alluded to in many
technical speci?- cations but are often not understood suf?ciently to take full
advantage of their potential. What is a 200-MHz superscalar RISC processor
with a four-way set associative cache? Some people hear the term RISC and
conjure up thoughts of high-performance computing. Such imagery is not
incorrect, but RISC technology can also be purchased for less than one dollar.
Caching is another big computer term that is more common than many people
think.

An important theme to keep in mind is that microprocessors and the systems
that they plug into are inextricably interrelated, and more so than simply by
virtue of their common physical surround- ings. The architecture of one
directly in?uences the capabilities of the other. For this reason, the two need
to be considered simultaneously during the design process. Among many
other factors, this makes computer design an iterative process. One may
begin with an assumption of the type of mi- croprocessor required and
then use this information to in?uence the broader system architecture.

When system-level constraints and capabilities begin to come into focus,
they feed back to the microprocessor requirements, possibly altering them
somewhat. This cycle can continue for several iterations until a design is
realized in which the microprocessor and its supporting peripherals are
well matched for the application.

By : E-book Complete_Digital_Design

Following their success in the microprocessor market, Intel began manufacturing
microcontrollers in 1976 with the introduction of the 8048 family. This early
microcontroller contains 64 bytes of RAM, 1 kB of ROM, a simple 8-bit
microprocessor core, and an 8-bit timer/counter as its sole on-board peripheral.
(Subsequent variants, the 8049 and 8050, include double and four times the
memory of the 8048, respectively.) The microprocessor consists of a 12-bit
program counter, an 8-bit accumulator and ALU, and a 3-bit stack pointer.
The 8048 is a complete computer on a single chip and gained a certain amount
of fame in the 1980s when it was used as the standard keyboard controller
on the IBM PC because of its simplicity and low cost. The 8048 was
manufactured in a 40-pin DIP and could be expanded with external memory
and peripherals via an optional external address/data bus. However, when
operated as a nonexpanded single-chip computer, the pins that would
otherwise function as its bus were available for general I/O purposes a
practice that is fairly standard on microcontrollers.

Motivated by the popularity of the 8048, Intel introduced the 8051 microcontroller
in 1980, which is substantially more powerful and ?exible. The 8051s basic
architecture is shown in Fig. 6.3. It contains 128 bytes of RAM, 4 kB of ROM,
two 16-bit timer/counters, and a serial port. Registers within the microprocessor
are 8 bits wide except for the 16-bit data pointer (DPTR) and program counter
(PC). Memory is divided into mutually exclusive program and data sections that
each can be expanded up to 64 kB in size via an external bus. Expansion is
accomplished by borrowing pins from two of the four 8-bit I/O ports. Intel
manufactured several variants of the 8051. The 8052 doubled the amount
of on-chip memory to 256 bytes of RAM and 8 kB of ROM and added a
third timer. The 8031/8032 are 8051/8052 chips without on-board ROM.
The 8751/8752 are 8051/8052 devices with EPROM instead of mask ROM.
As time went by and the popularity of the 8051 family increased, other
companies licensed the core architecture and developed many variants with
differing mixes of memory and peripherals.

Ports 0 through 3 are each eight-bit bidirectional I/O structures that can be used
as either generalpurpose signals or as dedicated interface signals according to
the system con?guration. In a single-chip con?guration where all memory is
contained on board, the four ports may be assigned freely. Some peripheral
functions use these I/O pins, but if a speci?c function is not required, the pins
may be used in a generic manner. Port 3 is the default peripheral port where
pins are used for the serial ports transmit and receive, external interrupt
request inputs, counter increment inputs, and external bus expansion control
signals. Port 1 is a general-purpose port that is also assigned for additional
peripheral support signals when an 8051 variant contains additional peripheral
functions beyond what can be supported on port 3 alone.

In a multichip con?guration where memory and/or additional peripherals are
added externally, ports 0 and 2 are used for bus expansion. Port 0 implements
a multiplexed address/data bus where the 8051 ?rst drives the lower eight
address bits and then either drives write-data or samples read-data in a
conventional bidirectional data bus scheme. In this standard con?guration,
the lower ad- dress bits, A[7:0], are latched externally by a discrete logic
chip (generally a 74LS373 or similar), and the 8051 drives an address latch
enable (ALE) signal to control this latch as shown in Fig. 6.4. This multiplexed
address/data scheme saves precious pins on the microcontroller that can be
used for valuable I/O functions. Some applications may suf?ce with just an
eight-bit external address bus. For example, if the only expansion necessary
were a special purpose I/O device, 256 bytes would probably be more than
enough to communicate with the device. However, some applications
demand a fully functional 16-bit external address bus. In these situations,
port 2 is used to drive the upper address bits, A[15:8].

FIGURE 6.3 8051 overall architecture.

FIGURE 6.4 8051 system with external address latch.

The 8051s microprocessor is very capable for such an early microcontroller.
It includes integer multiply and divide instructions that utilize eight-bit operands
in the accumulator and B register, and it then places the result back into those
registers. The stack, which grows upward in memory, is restricted to on-board
RAM only (256 bytes at most), so only an eight-bit stack pointer is implemented
. Aside from the general-purpose accumulator and B registers, the 8051
instruction set can directly reference 8 byte-wide general-purpose registers,
numbered R0 through R7, that are mapped as 4 banks in the lower 32 bytes
of on-board RAM. The active register bank can be changed at any time by
modifying two bank-select bits in the status word. The map of on-board data
memory is shown in Table 6.2. At reset, register bank 0 is selected, and the
stack pointer is set to 0×07, meaning that the stack will actually begin at
location 0×08 when the ?rst byte is eventually pushed. Above the register
banks is a 16-byte (128-bit) region of memory that is bit addressable.
Microcontroller applications often involve reading status information, checking
certain bits to detect particular events, and then triggering other events. Using
single bits rather than whole bytes to store status information saves precious
memory in a microcontroller. Therefore, the 8051s bit manipulation
instructions can make ef?cient use of the chips resources from both instruction
execution and memory usage perspectives. The remainder of the lower
128-byte memory region contains 80 bytes of general-purpose memory.

The upper 128 bytes of data memory are split into two sections: special-function
registers and RAM. Special-function registers are present in all 8051 variants,
but their de?nitions change according to the speci?c mix of peripherals in each
variant. Some special-function registers are standard across all 8051 variants.
These registers are typically those that were implemented on the original
8051/8052 devices and include the accumulator and B registers; the stack
pointer; the data pointer; and serial port, timer, and I/O port control registers.
Each time a manufacturer adds an on-board peripheral to the 8051,
accompanying control registers are added into the special-function
memory region.

On variants that incorporate 256 bytes of on-board RAM, the upper 128 bytes
are also mapped into a parallel region alongside the special-function registers.
Access between RAM and special-function registers is controlled by the
addressing mode used in a given instruction. Special-function registers are
accessed with direct addressing only. Therefore, such an instruction must
follow the opcode with an eight-bit address. The upper 128 bytes of RAM
are accessed with indirect addressing only. Therefore, such an instruction
must reference one of the eight general-purpose registers (R0 through R7
in the currently selected bank) whose value is used to index into that portion
of RAM. The lower 128 bytes of RAM are accessible via both direct and
indirect addressing.

The 8051 is a good study in maximizing the capabilities of limited resources.
Access to external memory is supported through a variety of indirect and indexed
schemes that provide an option to the system designer of how extensive an
external bus is implemented. Indirect access to external data memory is
supported in both 8- and 16-bit address con?gurations. In the 8-bit mode,
R0 through R7 are used as memory pointers, and the resulting address is
driven only on I/O port 0, freeing port 2 for uses other than as an address bus.
The DPTR functions as a pointer into data memory in 16-bit mode, enabling
a full 64-kB indirect addressing range. Indexed access to external program
memory is supported by both the DPTR and the PC. Being program memory
(ROM), only reads are sup- ported. Both DPTR and PC can serve as index
base address registers, and the current value in the accumulator serves as an
offset to calculate a ?nal address of either DPTR+A or PC+A.

The 8051s external bus interface is asynchronous and regulated by four basic
control signals: ALE, program storage enable (PSEN*), read enable (RD*),
and write enable (WR*). Figure 6.5 shows the interaction of these four
control signals and the two bus ports: ports 0 and 2. Recall that ALE
causes an external latch to retain A[7:0] that is driven from port 0 during
the ?rst half of the access and prior to port 0 transitioning to a data bus
role. The timing delays noted are for a standard 12-MHz operating
frequency (the highest frequency supported by the basic 8051 devices,
although certain newer devices can operate at substantially faster frequencies).*

FIGURE 6.5 8051 bus interface timing.

Although the speci?c timing delays of program memory and data memory
reads are different, they exhibit the same basic sequence of events. (More
time is allowed for data reads than for instruction reads from program
memory.) Therefore, if the engineer properly accounts for the timing
variations by selecting memory and logic components that are fast
enough to satisfy the PSEN* and RD* timing speci?cations simultaneously,
program and data memory can actually be merged into a uni?ed memory
space external to the chip. Such uni?cation can be performed by generating
a general memory read enable, MRE*, that is the AND function of PSEN*
and RD*. In doing so, whenever either read enable is driven low by the
8051, MRE* will be low. This can bene?t some applications by turning
the 8051 into a more general-purpose computing device that can load a
program into its data memory and then execute that same program
from program memory. It also enables indexed addressing to operate
on data memory, which normally is restricted to indirect addressing as
discussed previously.

Timers such as those found in the 8051 are useful for either counting external
events or triggering low-frequency events themselves. Each timer can be
con?gured in two respects: whether it is a timer or counter, and how the
count logic functions. The selection of timer versus counter is a decision
between incrementing the count logic based on the microcontrollers
operating frequency or on an external event sensed via an input port pin.
The 8051s internal logic runs in a repetitive pattern of 12 clock cycles in
which 1 machine cycle consists of 12 clock cycles. Therefore, the count
logic increments once each machine cycle when in timer mode. When in
counter mode, a low-to-high transition (rising edge) on a designated input
pin causes the counter to increment. The counter can be con?gured to
generate an interrupt each time it rolls over from its maximum count value
back to its starting value. This interrupt can be used to either trigger a
periodic maintenance routine at regular intervals (timer mode) or to take
action once an external event has occurred a set number of times
(counter mode). If not con?gured to generate an interrupt, the software
can periodically poll the timer to see how many events have occurred
or how much time has elapsed.

The timers inherently possess two 8-bit count registers that can be con?gured
in a variety of ways as shown in Fig. 6.6. A timer can be con?gured as a
conventional 16-bit counter, as two 8-bit counters, as a single 8-bit counter
with a 5-bit prescaler, and as a single 8-bit counter with an 8-bit reload
value. The ?rst two modes mentioned are straightforward: the timers count
from 0 to either 65,535 (16-bit) or 255 (8-bit) before rolling over and
perhaps generating an interrupt. The third mode is similar, but the 8-bit
counter increments only once every 32 machine cycles. The 5-bit (2⁵ = 32)
prescaler functions as a divider ahead of the main counter. Apparently, the
main reason for in- cluding this mode was to retain function compatibility
with the 8048s prescaled timer. The fourth mode is interesting, because
the 8-bit counter is reloaded with an arbitrary 8-bit value rather than 0 after
reaching its terminal count value (255). When operated in timer mode, this
feature enables the timer to synthesize a wide range of low-frequency periodic
events. One very useful periodic event is an RS-232 bit-rate generator. A
commonly observed 8051 operating frequency is 11.0592 MHz. When
this frequency is divided by 12, a count increment rate of 921.6 kHz is
obtained. Further dividing this frequency by divisors such as 96 or 384
yields the standard RS-232 bit rates 9.6 kbps and 2.4 kbps. A divisor
of 384 cannot be implemented in an 8-bit counter. Instead, a selectable ?16
or ?32 counter is present in the serial port logic that generates the ?nal serial
bit rate.

FIGURE 6.6 8051 timer con?gurations.

The 8051s on-board serial port implements basic synchronous or asynchronous
transmit and receive shift-register functionality but does not incorporate hardware
handshaking of the type used in RS-232 communications. Serial transmission is
initiated by writing the desired data to a transmit register. Incoming data is
placed into a receive register, and an interrupt can be triggered to invoke a
serial port ISR. The serial port can be con?gured in one of four modes, two of
which are higher-fre-quency ?xed bit rates, and two of which are
lower-frequency variable bit rates established by the rollover characteristics
of an on-board timer. Mode 0 implements a synchronous serial interface
where the receive data pin is actually bidirectional and a transmit clock
is emitted on the transmit data pin. This mode operates on 8-bit data
and a ?xed bit rate of 1/12 the operating frequency.

Mode 1 implements an asynchronous transmit/receive serial port where ten
bits are exchanged for every byte: a start bit, eight data bits, and a stop bit.
The bit-rate is variable according to a timer rollover rate. Mode 3 is very
similar to mode 1, with the added feature that a ninth data bit is added to
each byte. This extra data bit can be used for parity in an RS-232
con?guration or for another application-speci?c purpose. These two
modes can be used to implement an RS-232 serial port without hardware
handshaking. Software-assisted hardware handshaking could be added
using general I/O pins on the 8051. Mode 2 is identical to mode 3 except
for its ?xed bit rate at either 1/32 or 1/64 the operating frequency. Modes
1 and 3 can be made to operate at standard RS-232 bit rates from
19.2 kbps on downward with the aforementioned 11.0592 MHz operating
frequency. A selectable ?16 or ?32 counter within the serial port logic
combines with the timer rollover to achieve the desired serial bit rate.

Intels 8051 architecture has been designed into countless applications in which
a small, embed- ded computer is necessary to regulate a particular process.
The original 40-pin devices are still commonly used and found in distributors
warehouses, but a host of newer devices are popular as well. Some of these
variants are larger and more capable than the original and include more
I/O ports, on- board peripherals, and memory. Some variants have taken
the opposite direction and are available in much smaller packages
(e.g., 20 pins) with low power consumption for battery-powered applications.
There are even special versions of the 8051 that are radiation hardened for
space and military applications. Companies that manufacture 8051 variants
include Atmel, Maxim (formerly Dallas Semiconductor), and Philips. Atmel
manufactures a line of small, low-power 8051 products. Maxim offers a
selection of high-speed 8051 microcontrollers that run at up to 33 MHz
with a 4-cycle architecture, as compared to 12 in the original 8051. Philips
has a broad 8051 product line with a variety of peripherals to suit many
individual applications.

The mature ROM-less 8031/8032 members of the 8051 family can be
ordered through many mail order retail electronics outlets for only a few
dollars apiece. The equally mature 8751/8752 EPROM devices can also
be found from many of these same sources, though at a higher price as a
result of the expense of the ceramic DIP in which they are most often
found. More specialized 8051 variants may be available only through
manufacturers authorized distributors.

By : E-book Complete_Digital_Design

Even though modem speed hasn’t changed since 1998, modems have gotten better. You might recall that picking up a telephone while an early 56K modem was connected to the Internet on the same line caused the modem to instantly disconnect the connection. Fortunately, that problem was abated in subsequent modems.

Modem Removal and Installation

External modems are simple to install; just plug in and install the software, with the order depending on the instructions to the particular model. Internal modems are installed physically just as any other expansion card. Many will be installed automatically by Windows.

Software that uses modems, such as faxing programs or dial-up Internet software like AOL, have provisions to search for the modem. Therefore, it is a good idea to look in Device Manager to see how many COM ports are installed in the machine. Look for the Ports (COM & LPT) listing and click the plus sign. Hopefully, you won’t see any more than the number of physical COM ports installed on the system. Then, when you install the modem or modem-using software, look for the COM port the system uses. If the port number is the same as one of the physical COM ports, it is usually wise to change it. To do this, open up Modem Properties in Device Manager or in Control Panel > Phone and Modem (or equivalent). Click the Advanced tab to get a page similar to the one shown in Figure 8.8.

Figure 8.8: Advanced modem properties.

If you change it, make sure to change it in modem-using software too. Then, check all programs that use the modem: dial-up Internet, telephone networking, telephone dialing and answering systems, and fax programs. Either change the COM port manually in these or have the programs redetect the modem.

By : Book-PC Repair and Maintenance: A Practical Guide

As the microprocessor market began to take off, Motorola jumped into the fray
and introduced its eight-bit 6800 in 1974, shortly after the 8080 ?rst appeared.
While no longer available as a discrete microprocessor, the 6800 is signi?cant,
because it remains in Motorolas successful 68HC05/68HC08 and 68HC11
microcontroller families and also serves as a vehicle with which to learn the
basics of computer architecture. Like the 8080, the 6800 is housed in a 40-pin
DIP and features a 16-bit address bus and an 8-bit data bus. All of the basic
register types of a modern microprocessor are implemented in the 6800, as
shown in Fig. 6.1: a program counter (PC), stack pointer (SP), index register
(X), two general-purpose accumulators (ACCA and ACCB), and status
?ags set by the ALU in the condition code register (CCR). ACCA is the
primary accumulator, and some instructions oper- ate only on this register
and not ACCB. A half-carry ?ag is included to enable ef?cient binary coded
decimal (BCD) operations. After adding two BCD values with normal binary
arithmetic, the half- carry is used to convert illegal results back to BCD. The
6800 provides a special instruction, decimal adjust ACCA (DAA), for this
speci?c purpose. A somewhat out-of-place interrupt mask bit is also
implemented in the CCR, because this was an architecturally convenient place
to locate it. Bits in the CCR are modi?ed through either ALU operations or
directly by transferring the value in ACCA to the CCR.

The 6800 supports three interrupts: one nonmaskable, one maskable, and
one software interrupt. More recent variants of the 6800 support additional
interrupt sources. A software interrupt can be used by any program running
on the microprocessor to immediately jump to some type of maintenance
routine whose address does not have to be known by the calling program.
When the software interrupt instruction is executed, the 6800 reads the
appropriate interrupt vector from memory and jumps to the indicated address.
The 6800s reset and interrupt vectors are located at the top of memory, as
listed in Table 6.1, which generally dictates that the boot ROM be located
there as well. For example, an 8-kB 27C64 EPROM
(8,192 bytes = 0×2000 bytes) would occupy the address range 0xE000
through 0xFFFF. Each vector is 16 bits wide, enough to specify the full
address of the associated routine. The MSB of the address, A[15:8], is
located in the low, or even, byte address, and the LSB, A[7:0] is located
in the high, or odd, byte address.

FIGURE 6.1 6800 registers.

An external clock driver circuit that provides a two-phase clock (two clock
signals 180? out of phase with respect to each other) is required for the original
6800. Motorola simpli?ed the design of 6800-based computer systems by
introducing two variants, the 6802 and 6808. The 6802 includes an on-board
clock driver circuit of the type that is now standard on many microprocessors
available today. Such clock drivers require only an external crystal to create
a stable, reliable oscillator with which to clock the microprocessor. A crystal
is a two-leaded component that contains a specially cut quartz crystal.
The quartz can be made to resonate at its natural frequency by electrical
stimulus cre- ated within the microprocessors on-board clock driver circuitry.
A crystal is necessary for this pur- pose, because its oscillation frequency is
predictable and stable. The 6802 also includes 128 bytes of on-board RAM
to further simplify certain systems that have small volatile memory requirements.
For customers who wanted the simpli?ed clocking scheme of the 6802
without paying for the on-board RAM, Motorolas 6808 kept the clocking
and removed the RAM.

Using a 6802 with its internal RAM, a functional computer could be constructed
with only two chips: the 6802 and an EPROM. Unfortunately, such a computer
would not be very useful, because it would have no I/O with which to interact
with the outside world. Motorola manufactured a variety of peripheral chips
intended for direct connection to the 6800 bus. Among these were the 6821
peripheral interface adapter (PIA) and the 6850 asynchronous communications
interface adapter (ACIA), a type of UART. The PIA provides 20 I/O signals
arranged as two 8-bit parallel ports, each with two control signals. Applications
including basic pushbutton sensing and LED driving are easy with the 6821.
The 6800 bus uses asynchronous control signals, meaning that memory and
I/O devices do not explicitly require access to the microprocessor clock to
communicate on the bus. However, many of the 6800 peripherals require
their own copy of the clock to run internal logic.

As with all synchronous logic, the 6800s bus is internally controlled by the
microprocessor clock, but the nature of the control signals enables asynchronous
read and write transactions without referencing that clock, as shown in Fig. 6.2.
An address is placed onto the bus along with the proper state of the R/W
select signal (read = 1, write = 0) and a valid memory address (VMA) enable
that indicates an active bus cycle. In the case of a write, the write data is
driven out some time later. For reads, the data must be returned fast enough
to meet the microprocessors timing speci?cations. The 6802/6808 were
manufactured in 1-, 1.5-, and 2-MHz speed grades. At 2 MHz, a peripheral
device has to respond to a read request with valid data within 210 ns after
the assertion of address, R/W, and VMA. A peripheral has up to 290 ns
from the assertion of these signals to complete a write transaction.

*In a real system, VMA, combined with address decoding logic, would drive
the individual chip select signals to each peripheral.

In some situations, slow peripherals may be used that cannot execute a bus
transaction in the time allowed by the microprocessor. The 6800 architecture
deals with this by stretching the clock during a slow bus cycle. A clock
cycle can be stretched as long as 10 ?s, enabling extremely slow peripherals
by delaying the next clock edge that will advance the microprocessors
internal state and termi- nate a pending bus cycle. This stretching is
performed by an external clock circuit for a 6800, or by the internal clock
of the 6802/6808. As with many modern microprocessors, the 6802/6808
provides a pin that delays the end of the current bus cycle. This memory
ready (MR) signal is normally high, signaling that the addressed device is
ready. When brought low, the clock is internally stretched until MR goes
high again. Early microprocessors such as the 6800 used clock stretching
to delay bus cy- cles. Most modern microprocessors maintain a constant
clock frequency and, instead, insert discrete wait states, or extra clock
cycles, into a bus transaction when a similar type of signal is asserted.
This latter method is usually preferable in a synchronous system because
of the desire to maintain a simple clock circuit and to not disrupt other
logic that may be running on the microprocessor clock.

FIGURE 6.2 6802/6808 basic bus timing.

Motorolas success with the 6800 motivated it to introduce the upgraded 6809
in 1978. The 6809 is instruction set compatible with the 6800 but includes
several new registers that enable more ?exi- ble access to memory. Two stack
pointers are present: the existing hardware controlled register for subroutine
calls and interrupts, and another for user control. The user stack pointer can
be used to ef?ciently pass parameters to subroutines as they are called without
con?icting with the microprocessors push/pop operations involving the
program counter and other registers. A second index register and the ability
to use any of the four 16-bit pointer registers as index registers were added
to enable the simultaneous handling of multiple data structure pointers without
having to continually save and recall index register values. The 6809s two
accumulators can be concatenated to form a 16-bit accumulator that enables
16-bit arithmetic with an enhanced ALU. This ALU is also capable of eight-bit
unsigned multiplication, which made the 6809 one of the ?rst integrated
microprocessors with multiplication capability.

Other improvements in the 6809 included a direct page register (DPR) for a
more ?exible eight- bit direct addressing mode. The 8-bit DPR, representing
A[15:8], is combined with an 8-bit direct address, representing A[7:0], to
form a 16-bit direct address, thereby enabling an 8-bit direct address to
reference any location in the complete 64-kB address space. The 6809 also
included a more advanced bus interface with direct support for an external
DMA controller. Several desktop computers, including the Tandy/Radio
Shack TRS-80 Color Computer, and various platforms, including arcade
games, utilized the 6809.

While still available from odd-lot retail outlets, the original 6800 family members
are no longer practical to use in many computing applications. Their capabilities,
once leading edge, are now available in smaller, more integrated ICs at lower
cost and with lower power consumption. However, the 6800 architecture is
alive and well in the 68HC05/68HC08 and 68HC11 microcontroller families
that are based on the 6800/6802/6808 and 6809 architectures, respectively.
These microcontrollers are available with a wide range of integrated features
with on-board RAM, ROM (mask ROM, EE-PROM, or EPROM), serial
ports, timers, and analog-to-digital converters.

By : E-book Complete_Digital_Design

Oddly, modems are often confused with the computer itself. A modem, as discussed in this chapter, is a device that connects a computer to a standard analog telephone line, the kind to which your telephone is connected. Modems are used for dial-up Internet service, telephone use such as faxing, wide area network (WAN) connections, and the antiquated, but still-used terminal connections, which are beyond the scope of this book. You might have noticed that modem speed has been stuck at a maximum of 56 Kbps for several years. That is because the amount of data that can be transmitted across an analog telephone line might have reached a physical limit. Consequently, although there have been improvements in accuracy of data transfer and the capability of connecting and holding onto a telephone line, modems haven’t gotten any faster than 56K. Because of this limit, Internet service has moved away from dial-up and toward different broadband technologies. As a result, modems are now not usually built into newer motherboards (except in laptops, which are often used where the only network access is through telephone lines). There are a few motherboards out there with modem risers. These are slots that take proprietary modem cards. If one of these modems fails, it is cheapest and easiest to remove it and install a standard modem in a PCI or ISA slot, if possible.

Internal vs. External Modems

Internal modems are PCI or ISA expansion cards. They tend to be simple to install; just follow the manufacturer’s directions if available. They receive their power from the slot. External modems are less common today, but are still around because internal modems are often optional these days. External modems traditionally plug into a serial port on the computer, although there are USB modems available today as well. The advantages to external modems are that you don’t have to be a technician to install one and they can easily be moved from computer to computer. The disadvantages to serial-port external modems are that they require external power and are more expensive. Most or all USB modems are powered by the USB ports and aren’t as expensive as serial port modems. Figure 8.6 shows a PCI modem, a USB modem, and an external serial port modem.

Figure 8.6: Three different types of modems.

PC-Card modems are designed for laptops without built-in modems, or those whose built-in modems are broken. They tend to be expensive. Many of these come with dongles, which are small cable assemblies that connect the card to the telephone jack assembly. Dongles are usually delicate and replacements have to be ordered from the manufacturer. Better designs are available that have the phone jacks built into the card. Figure 8.7 shows two PC-Card modems.

Figure 8.7: PC-Card modems.

Tip

For an alternative to PC-Card modems, try an external USB modem.

Following the 4004s introduction in 1971, Intel enhanced the four-bit architecture
by releasing the 4040 and 8008 in rapid succession. The 4040 added several
instructions and internal registers, and the 8008 extended the basic architecture
to eight bits. These processors ran at speeds from 100 to 200 kHz and were
packaged in 16 (4004/4040) and 18 (8008) pin DIPs. While signi?cant for their
time, they had limited throughput and could address only 4 kB (4004/4040)
or 16 kB (8008) of memory. In 1974, Intel made substantial improvements
in microprocessor design and released the 8080, setting the stage for modern
microprocessors. Whereas Intels earlier microprocessors look like relics of
a bygone era, the 8080 is architecturally not far off from many microprocessors
that exist today. The 8080 was housed in a 40-pin DIP, featured a 16-bit
address bus and an 8-bit data bus, and ran at 2 MHz. It also implemented a
conventional stack pointer that enabled deep stacks in external memory
(Intels earlier microprocessors had internal stacks with very limited depth).
The 8080 became extremely popular as a result of its performance and rich,
modern instruction set. This popularity was evidenced two years later,
in 1976, with Intels enhanced 8085 and competitor Zilogs famous Z80.
Designed by former Intel engineers, the Z80 was based heavily on the
8080 to the point of having a partially compatible instruction set.

Both the 8085 and Z80 were extremely popular in a variety of computing
platforms from hobbyists to mainstream commercial products to video
arcade games. The 8085 architecture in?uenced the famous 16-bit 8086
family whose strong in?uence continues to this day in desktop PCs.
The Z80 eventually lost the mainstream microprocessor war and migrated
to microcontrollers that are still available for new designs from Zilog.

As microprocessors progress, technologies that used to be leading edge ?rst
become mainstream and then appear quite pedestrian. Along the way, some
microprocessor families branch into multiple product lines to suit a variety
of target applications. The high-end computing market gets most of the
publicity and accounts for the major technology improvements over time.
Lower-end microprocessors are either made obsolete after some time
or ?nd their way into the embedded market. Embedded microprocessors
and systems are those that may not appear to the end user as a
computer, or they may not be visible at all. Instead, embedded
microprocessors typically serve a control function in a machine or another
piece of equipment. This is in contrast to the traditional computer with
a keyboard and monitor that is clearly identi?ed as a general-purpose
computer.

Integrated microprocessor products are called microcontrollers, a term that
has already been in- troduced. A microcontroller is a microprocessor
integrated with a varying mix of memory and peripherals on a single chip.
Microcontrollers are almost always found in embedded systems. As with
many industry terms, microcontrollers can mean very different things to
different people. In general, a microcontroller contains a relatively
inexpensive microprocessor core with a complement of on-board
peripherals that enable a very compact, yet complete, computing system
either on a single chip or relatively few chips. There is a vast array of
single-chip microcontrollers on the market that integrate quantities of
both RAM and ROM on the same chip along with basic peripherals
including serial communications controllers, timers, and general I/O signal
pins for controlling LEDs, relays, and so on. Some of the smallest
microcontrollers can cost less than a dollar and are available in packages
with as few as eight pins. Such devices can literally squeeze a complete
computer into the area of a ?ngernail. More complex microcontrollers
can cost tens of dollars and provide external mi- croprocessor buses for
memory and I/O expansion. At the very high end, there are microcontrollers
available for well over $100 that include 32-bit microprocessors running
at hundreds of megahertz, with integrated Ethernet controllers and DMA.
Manufacturers typically refer to these high-end microcontrollers with unique,
proprietary names to differentiate them from the aforementioned class
of inexpensive devices.

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