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Motorola followed its 6800 family by leaping directly to a hybrid 16/32-bitmicroprocessor architecture. Introduced in 1979, the 68000 is a 16-bitmicroprocessor, due to its 16-bit ALU, but it contains all 32-bit registers anda linear, nonsegmented 32-bit address space. (The original 68000 did notbring out all 32 address bits as signal pins but, more importantly, there are noarchitectural limitations of using all 32 bits.) That the register and memoryarchitecture is inherently 32 bits made the 68000 family easily scalable toa full 32-bit internal architecture. Motorola upgraded the 68000 family withtrue 32-bit devices, including the 68020, 68040, ja 68060, until switchingto the PowerPC architecture in the latter portion of the 1990s for newhigh-performance computing applications. Apple Computer used the 68000family in their popular line of Macintosh desktop computers. Today, the68000 family lives on primarily as a mid-level embedded-processor coreproduct. Motorola manufacturers a variety of high-end microcontrollersthat use 32-bit 68000 microprocessor cores. However, in recent yearsMotorola has begun migrating these products, as well as their general-purposemicroprocessors, to the PowerPC architecture, reducing the number of newdesigns that use the 68000 family.
The 68000 inherently supports modern software operating systems (OSs)by recognizing two modes of operation: supervisor mode and user mode.A modern OS does not grant unlimited access to application software inusing the computers resources. Rather, the OS establishes a restrictedoperating environment into which a program is loaded. Depending on thespeci?c OS, applications may not be able to access certain areas of memoryor I/O devices that have been declared off limits by the OS. This can preventa fault in one program from crashing the entire computer system. The OSkernel, the core low-level software that keeps the computer running properly,has special privi- leges that allow it unrestricted access to the computer forthe purposes of establishing all of the rules and boundaries under whichprograms run. Hardware support for multiple privilege levels is crucial forsuch a scheme to prevent unauthorized programs from freely accessing restrictedresources. As microprocessors developed over the last few decades, morehardware support for OS privileges was added. That the 68000 included suchconcepts in 1979 is a testimony to its scalable architecture.
Sixteen 32-bit general-purpose registers, one of which is a user stack pointer(USP), and an 8-bit condition code register are accessible from user mode asshown in Fig. 6.11. Additionally, a supervisor stack pointer (SSP) and eightadditional status bits are accessible from supervisor mode. Computer systemsdo not have to implement the two modes of operation if the application doesnot require it. In such cases, the 68000 can be run permanently in supervisormode to enable full access to all resources by all programs. The SSP is usedfor stack operations while in supervisor mode, and the USP is used for stackoperations in user mode. User mode programs cannot change the USP,preventing them from relocating their stacks. Most modern operating systemsare multitasking, mean- ing that they run multiple programs simultaneously. Inreality, a microprocessor can only run one program at a time. A multitaskingOS uses a timer to periodically interrupt the microprocessor, perhaps 20 to100 times per second, and place it into supervisor mode. Each time supervisormode is invoked, the kernel performs various maintenance tasks and swapsthe currently running program with the next program in the list of running programs.This swap, or context switch, can entail substantial modi?cations to themicroprocessors state when it returns from the kernel timer interrupt. In thecase of an original 68000 microprocessor, the kernel could change the returnvalue of the PC, USP, the 16 general-purpose registers, and the status register.When normal execution resumes, the microprocessor is now executing adifferent program in exactly the same state at which it was previously interrupted,because all of its registers are in the same state in which they were left. In such ascenario, each program has its own private stack, pointed to by akernel-designated stack pointer.
The eight data registers, D0D7, can be used for arbitrary ALU operations. Theeight address registers, A0A7, can all be used as base addresses for indirectaddressing and for certain 16- and 32-bit ALU operations. All 16 registers canbe used as index registers. While operating in user mode, it is illegal to accessthe SSP or the supervisor portion of the status register, SR. Such instructions willcause an exception, whereby a particular interrupt is asserted, which causes the68000 to enter supervisor mode to handle the fault. (Exception and interrupt areoften used synonymously in computer contexts.) Very often, the OS kernel willterminate an application that causes an exception to be generated. The registersshown above are present in all 68000 family members and, as such, aresoftware is compatible with subsequent 68xxx microprocessors. Newermicroprocessors contain additional registers that provide more advanced privilegelevels and memory management. While the 68000 architecture fundamentallysupports a 4-GB (32-bit) address space, early devices were limited in termsof how much physical memory could actually be addressed as a result of pinlimitations in the packaging. The original 68000 was housed in a 64-pin DIP,leaving only 24 address bits usable, for a total usable memory space of 16 MB.When Motorola introduced the 68020, the ?rst fully 32-bit 68000 microprocessor,all 32 address bits were made available. The 68000 devices are big-endian,so the MSB is stored in the lowest address of a multibyte word.

The 68000 supports a 16-MB address space, but only 23 address bits, A[23:1],are actually brought out of the chip as signal pins. A[0] is omitted and is unnecessary,because it would specify whether an even (A[0] = 0) or odd (A[0] = 1) byte isbeing accessed; ja, because the bus is 16 bits wide, both even and odd bytescan be accessed simultaneously. However, provisions are made for byte-wideaccesses in situations where the 68000 is connected to legacy eight-bit peripheralsor memories. Two data strobes, upper (UDS*) and lower (LDS*), indicatewhich bytes are being ac- cessed during any given bus cycle. These strobes aregenerated by the 68000 according to the state of the internal A0 bit andinformation on the size of the requested transaction. Bus transactions aretriggered by the assertion of address strobe (AS*), the appropriate data strobes,and R/W* as shown in Fig. 6.12. Prior to AS*, the 68000 asserts the desiredaddress and a three-bit function code bus, FC[2:0]. The function code busindicates which mode the processor is in and whether the transaction is aprogram or data access. This information can be used by external logic toqualify transactions to certain sensitive memory spaces that may be off limitsto user programs. When read data is ready, the external bus interface logicasserts data transfer acknowledge (DTACK*) to inform the microprocessorthat the transaction is complete. As shown, the 68000 bus can be operated ina fully asyn-chronous manner. When operated asynchronously, DTACK* isremoved after the strobes are removed, ensuring that the 68000 detected theassertion of DTACK*. If DTACK* is removed prior to the strobes, thereis a chance of marginal timing where the 68000 may not properly detect theacknowledge, and it may wait forever for an acknowledge that has nowpassed. Writes are very similar to reads, with the obvious difference thatR/W* is brought low, and data is driven by the 68000. Another differenceis that the data strobe assertion lags that of AS*.

Advanced microprocessors such as the 68000 are designed to recognize faultconditions wherein the requested bus transaction cannot be completed. A busfault can be caused by a variety of problems, including unauthorized access(e.g., user mode tries to write to a protected supervisor data space) or anaccess to a section of memory that is not ?lled by a memory or peripheraldevice. Software should never access areas of memory that are off limits,because the results are unpredictable. Therefore, rather than simply issuinga false DTACK* and continuing with normal operation, the 68000 containsa bus error signal (BERR*) that behaves like DTACK* but triggers anexception rather than continuing normal execution. It is the responsibility ofexternal logic to manage the DTACK* and BERR* signals according tothe speci?c con?guration and requirements of the particular system.Operating the 68000 bus in an asynchronous manner is easy, but it reducesits bandwidth, because delays must be built into the acknowledge process toguarantee that both the 68000 and the interface logic maintain synchronization.Figure 6.12 shows read data being asserted prior to DTACK* and anarbitrary delay between the release of AS* and that of DTACK*. The datadelay is necessary to guar- antee that the 68000 will see valid data when itdetects a valid acknowledge. The second delay is necessary to ensure thatthe 68000 completes the transaction, as noted previously. These delays canbe eliminated if the bus is operated synchronously by distributing themicroprocessor clock to the interface logic and guaranteeing that varioussetup and hold timing requirements are met as speci?ed by Motorola. Insuch a con?guration, it is known from Motorolas data sheet that the68000 looks for DTACK* each clock cycle, starting at a ?xed time afterasserting the strobes, and then samples the read-data one cycle after detectingDTACK* being active. Because synchronous timing rules are obeyed,it is guaranteed that the 68000 properly detects DTACK* and, therefore,DTACK* can be removed without having to wait for the removal of thestrobes. 68000 synchronous bus timing is shown in Fig. 6.13, where eachtransaction lasts a minimum of four clock cycles. A four-cycle transactionis a zero wait state access. Wait states can be added by simply delayingthe assertion of DTACK* to the next cycle. However, to maintain propertiming, DTACK* (and BERR* and read-data) must always obey propersetup and hold requirements. As shown in the timing diagram, eachsignal transition, or edge, is time-bounded relative to a clock edge.Read timing allows a single clock cycle between data strobe assertion and thereturn of DTACK* for a zero wait-state transaction. However, zero wait-statewrites require DTACK* assertion at roughly the same time as the data strobes.Therefore, the bus interface logic must make its decision on asserting DTACK*based on the requested address when AS* is asserted. If the requested deviceis operational, DTACK* can be immediately asserted for a fast transaction.Unlike reads, where the microprocessor must wait for a device to return data,writes can be acknowledged before they are actually transferred to the device.In such a scheme, writes are posted within the bus interface logic.One or two cycles later, when the device accepts the posted write data, thebus interface logic ?nally completes the transaction without having delayedthe microprocessor. If completion of the posted- write transaction takeslonger than a few cycles, it could force a subsequent access to the samedevice to incur wait states. Either a read or a write would be blockeduntil the original write was able to complete, thus freeing the device tohandle the next transaction.

In addition to the basic bus interface, the 68000 supports bus arbitration toenable DMA or other logic to use the microprocessor bus for arbitrary applications.A bus request (BR*) signal is asserted by a device that wants to temporarily gaincontrol of the bus. On the next clock cycle, when the microprocessor is notinhibited by other operations, it asserts a bus grant (BG*) signal and places itsaddress, data, and control signals into tri-state so that they may be driven by theother device. The re- questing device then asserts bus grant acknowledge(BGACK*) to signal that it is controlling the bus, and it is then free to assertits own strobes, aadress, and data signals.
A variety of interrupts and exceptions are supported by the 68000. Some aretriggered as a result of instruction execution and some by external signals (e.g.,BERR* or an interrupt request). Examples of instruction exceptions are illegaluser mode register accesses or a divide-by-zero error. Most microprocessorsthat provide division capability contain some type of divide-by-zero errorhandling, because the result of such an operation is mathematically unde?nedand is usually the result of a fault in the program. The 68000 contains anexception vector table that is 1,024 bytes long and resides at the beginningof memory at address 0. In a multitasking system, the bus interface logic mayrestrict access to the vector table to supervisor mode only. In such a case, abus error could be triggered if a user mode program, indicated by FC[2:0],tried to write the table. Each of the 256 vector entries is four bytes longand provides the starting address of the associated ISR. The one deviationfrom this rule is the reset vector, which actually consists of two entries at wordaddresses 0 ja 4.
Upon reset, the 68000 fetches an initial PC value from address 4 and an initialSSP value from address 0. Vectors 0 through 63 are assigned or reserved byMotorola for various hardware exceptions. Vectors 64 through 255 areassigned as user interrupt vectors. Like other microprocessors in its category,the 68000 supports bus vectoring of user interrupts where an external interruptcontroller asserts an interrupt number onto the data bus during an interruptacknowledge cycle performed by the 68000 in response to an interruptrequest. This interrupt number is multiplied by four and used to index intothe exception table to fetch the address of the appropriate ISR.