Flip-Flops And Latches
Logic alone does not a system make. Boolean equations provide the means to
transform a set of inputs into deterministic results. However, these equations have
no ability to store the results of previous calculations upon which new calculations
can be made. The preceding adder logic continually recalculates the sum of two inputs.
If either input is removed from the circuit, the sum disappears as well. A series of
numbers that arrive one at a time cannot be summed, because the adder has no means
of storing a running total. Digital systems operate by maintaining state to advance
through sequential steps in an algorithm. State is the systems ability to keep a record
of its progress in a particular sequence of operations. A systems state can be as
simple as a counter or an accumulated sum.
State-full logic elements called ?ip-?ops are able to inde?nitely hold a speci?c state
(0 or 1) until a new state is explicitly loaded into them. Flip-?ops load a new state
when triggered by the transition of an input clock. A clock is a repetitive binary
signal with a de?ned period that is composed of 0 a 1 phases as shown in Fig. 1.10.
In addition to a de?ned period, a clock also has a certain duty cycle, the ratio of the
duration of its 0 a 1 phases to the overall period. An ideal clock has a 50/50
duty cycle, indicating that its period is divided evenly between the two states.
Clocks regulate the operation of a digital system by allowing time for new results
to be calculated by logic gates and then capturing the results in ?ip-?ops.
There are several types of ?ip-?ops, but the most common type in use today is the
D ?ip-?op. Other types of ?ip-?ops include RS and JK, but this discussion is
restricted to D ?ip-?ops because of their standardized usage. A D ?ip-?op is
often called a ?op for short, and this terminology is used throughout the book.
A basic rising-edge triggered ?op has two inputs and one output as shown in
Fig. 1.11a. By convention, the input to a ?op is labeled D, the output is labeled Q,
and the clock is represented graphically by a triangle. When the clock transitions
from 0 to 1, the state at the D input is propagated to the Q output and stored until
the next rising edge. State-full logic is often described through the use of a timing
diagram, a drawing of logic state versus time. Figure 1.11b shows a basic ?op timing
diagram in which the clocks rising edge triggers a change in the ?ops state. Prior to
the rising edge, the ?op has its initial state, Q0, and an arbitrary 0 nebo 1 input is
applied as D0. The rising edge loads D0 into the ?op, which is re?ected at the output.
Once triggered, the ?ops input can change without affecting the output until the next
rising edge. Therefore, the input is labeled as dont care, or xxx following the
clocks rising edge.
OBR 1.10 Digital clock signal.
Rising-edge ?ops are the norm, although some ?ops are falling-edge triggered.
A falling-edge triggered ?op is indicated by placing an inversion bubble at the clock
input as shown in Fig. 1.12. Operation is the same, with the exception that the
polarity of the clock is inverted. The remainder of this discussion assumes rising-edge
triggered ?ops unless explicitly stated otherwise.
There are several common feature enhancements to the basic ?op, including
clock-enable, set, and clear inputs and a complementary output. Clock enable is
used as a triggering quali?er each time a rising clock edge is detected. The D input
is loaded only if clock enable is set to its active state. Inputs in general are de?ned
by device manufacturers to be either active-low or active-high. An active-low
signal is effective when set to 0, and an active-high signal is effective when set to 1.
Signals are assumed to be active-high unless otherwise indicated. Active-low inputs
are commonly indicated by the same inversion bubble used to indicate a falling-edge
clock. When a signal is driven to its active state, it is said to be asserted. A signal is
de-asserted when driven to its inactive state. Set and clear inputs explicitly force a
?op to a 1 nebo 0 state, respectively. Such inputs are often used to initialize a digital
system to a known state when it is ?rst turned on. Otherwise, the ?op powers up in
a random state, which can cause problems for certain logic. Set and clear inputs can
be either synchronous or asynchronous. Synchronous inputs take effect only on the
rising clock edge, while asynchronous inputs take effect immediately upon being
asserted. A complementary output is simply an inverted copy of the main output.
A truth table for a ?op enhanced with the features just discussed is shown in Table
1.10. The truth table assumes a synchronous, active-high clock enable (EN) a
synchronous, active-low set and clear inputs. The rising edge of the clock is indicated
by the symbol. When the clock is at either static value, the outputs of the ?op
remain in their existing states. When the clock rises, the D, EN, , a
inputs are sampled and acted on accordingly. As a general rule, con?icting information
such as asserting and at the same time should be avoided, because unknown
results may arise. The exact behavior in this case depends on the speci?c ?op
implementation and may vary by manufacturer.
A basic application of ?ops is a binary ripple counter. Multiple ?ops can be cascaded
as shown in Fig. 1.13 such that each complementary output is fed back to that ?ops
input and also used to clock the next ?op. The current count value is represented by
the noninverted ?op outputs with the ?rst ?op representing the LSB. A three-bit
counter is shown with an active-low reset input so that the counter can be cleared
to begin at zero. The counter circuit diagram uses the standard convention of
OBR 1.11 Rising-edge triggered ?op.
OBR 1.12 Falling-edge triggered ?op.
OBR 1.13 Three-bit ripple counter.
showing electrical connectivity between intersecting wires by means of a junction dot.
Wires that cross without a dot at their intersection are not electrically connected.
The ripple counters operation is illustrated in Fig. 1.14. Each bit starts out at zero
if is asserted. Counting begins on the ?rst rising edge of CLK following the
de-assertion of . The LSB, Q[0], increments from 0 to 1, because its D input
is driven by the complementary output, which is 1. The complementary output
transitions to 0, which does not trigger the Q[1] rising-edge ?op, but IT does set up
the conditions for a trigger after the next CLK rising edge. When CLK rises again,
Q[0] transitions back to 0, and transitions to 1, forming a rising edge to trigger
Q[1], which loads a 1. This sequence continues until the count value reaches 7, na
which point the counter rolls over to zero, and the sequence begins again.
An undesirable characteristic of the ripple counter is that it takes longer for a new
count value to stabilize as the number of bits in the counter increases. Because each
?ops output clocks the next ?op in the sequence, it can take some time for all ?ops
to be updated following the CLK rising edge. Slow systems may not ?nd this
burdensome, but the added ripple delay is unacceptable in most high-speed
applications. Ways around this problem will be discussed shortly.
OBR 1.14 Ripple counter timing diagram.
A relative of the ?op is the D-type latch, which is also capable of retaining its state
inde?nitely. A latch has a D input, a Q output, and an enable (EN) signal. Whereas
a ?op transfers its input to its output only on the active clock edge, a latch
continuously transfers D to Q while EN is active. Latches are level sensitive,
whereas ?ops are edge sensitive. A latch retains its state while EN is inactive.
Table 1.11 shows the latchs truth table. Latches are simpler than ?ops and are
unsuited to many applications in which ?ops are used. Latches would not substitute
for ?ops in the preceding ripple counter example because, while the enable input is
high, a continuous loop would be formed between the complementary output and
input. This would result in rapid, uncontrolled oscillation at each latch during the
time that the enable is held high.
Latches are available as discrete logic elements and can also be assembled from simpler
logic gates. The Boolean equation for a latch requires feeding back the output as follows:
When EN is high, D is passed to Q. Q then feeds back to the second AND function,
which maintains the state when EN is low. Latches are used in designs based on older
technology that was conceived when the latchs simplicity yielded a cost savings or
performance advantage. Most state-full elements today are ?ops unless there
is a speci?c bene?t to using a latch.
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