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Březen 20, 2010

Interpreting a Digital IC Data Sheet

Přidal: oprava  :  Kategorie: Integrovaných obvodů a 7400 Logické Rodiny
Semiconductor manufacturers publish data sheets for each of their products. Regardlessof the speci?c family or device, all logic IC data sheets share common types of information.Once the basic data sheet terminology and organization is understood, it is relatively easyto ?gure out other data sheets even when their exact terminology changes. Data sheetstructure is illustrated using the 74LS00 from Fairchild Semiconductor as an example.A page from its data sheet is shown in Fig. 2.19.
Digital IC data sheets should have at least two major sections: functional descriptionand electri- cal speci?cations. The functional description usually contains the device pinassignment, or pin-out, as well as a detailed discussion of how the part logically operates.A simple IC such as the 74LS00 will have a very brief functional description, becausethere is not much to say about a NAND gates operation. More complex ICs suchas microprocessors can have functional descriptions that ?ll dozens or hundreds ofpages and are broken into many chapters. Some data sheets add additional sectionsto present the mechanical dimensions of the package and its thermal properties.Digital IC electrical speci?cations are similar across most types of devices and oftenappear in the following four categories:
Absolutní maximální výkon. As the term implies, these parameters specify theabsolute extremes that the IC may be subjected to without sustaining permanent damage.Manufacturers almost uni- versally state that the IC should never be operated underthese extreme conditions. These ratings are useful, because they indicate how thedevice may be stored and express the quality of design and manufacture of the physicalchip. Manufacturers specify a storage temperature range within which the semiconductorstructures will not break down. In the case of Fairchilds 74LS00, this range is 65 to150?C. Maximum voltage levels are also speci?ed, 7 V in the case of the 74LS00,indicating that the device may be subjected to a 7-V potential without destructing.
Recommended operating conditions. These parameters specify the normal rangeof voltages and temperatures that the IC should be operated within such that itsfunctionality is guaranteed to meet speci?cations set forth by the manufacturer.Two of the most important speci?cations in this sec- tion are the supply voltage(commonly labeled as either VCC or VDD, depending on whether a bipolar or MOSprocess) and the operating temperature. An IC may have multiple supply voltagespeci?cations, because an IC can actually operate on several different voltagessimultaneously. Each supply voltage may power a different portion of the chip.When the manufacturer speci?es supply voltage, it does so with a certain tolerance,usually either ?5 nebo ?10 percent. Many 5-V logic ICs are guaranteed to operateonly at a supply voltage from 4.75 to 5.25 V (?5 percent). Operating temperatureis very important, because it affects the timing of the device. As a semiconductorheats up, it slows down. As it cools, its speed increases. Outside of therecommended operating temperature, the device is not guaranteed to function,because the effects of temperature become so severe that functionality iscompromised. There are four common temperature ranges for ICs: commercial(0 to 70?C), industrial (40 to 85?C), automotive (40 to 125?C), and military(55 to 125?C). It is more dif?cult to manufacture an IC that operates overwider temperature ranges. As such, more demanding temperature grades areoften more expensive than the commercial grade.
Other parameters establish the safe operating limits for input signals as well asthe applied volt- age thresholds that represent logic 0 a 1 states. Minimumand maximum input levels are ex- pressed as either absolute voltages or voltagesrelative to the supply voltage pins of the device. Exceeding these voltages maydamage the device. Logic threshold speci?cations are provided to ensure that thelogic input voltages are such that the device will function as intended and notconfuse a 1 for a 0, or vice versa. There is also a limit to how must currenta digital output can drive. Current output speci?cations should be known so thata chip is not overloaded, which could result in either permanent damage to thechip or the chips failure to meet its published speci?cations.

FIGURE 2.19 74LS00 manufacturers speci?cations.

OBR 2.19 74LS00 manufacturers speci?cations. (Reprinted with permission from Fairchild Semiconductor and National Semiconductor.)

DC electrical characteristics. DC parameters specify the voltages and currentsthat the IC will present to other circuitry to which it is connected. Whereas recommendedoperating conditions specify the environment under which the chip will properly operate,DC electrical characteristics specify the environment that the chip itself will create.Output voltage speci?cations de?ne the logic 0 a 1 thresholds that the chip isguaranteed to drive under all legal operating conditions. These speci?cations con?rmthat the chip is compatible with other chips in the same family and also allow anengineer to determine if the output levels are compatible with another chip that itmay be driving.
Input current speci?cations characterize the load that the chip presents to whatevercircuit is driving it. When either logic state is applied to the chip, a small current ?owsbetween the driver and the chip in question. Quantifying these currents enables anengineer to ensure compatibility between multiple ICs. When one IC drives severalother ICs, the sum of the input currents should not exceed the output currentspeci?cation of the driver.
AC electrical characteristics or switching characteristics). AC parameters oftenrepresent the greatest complexity and level of detail in a digital ICs speci?cations.They are the guaranteed timing parameters of inputs and outputs. If the IC is purelycombinatorial (e.g., 74LS00), timing may just be matter of specifying propagationdelays and rise and fall times. Logic ICs with syn- chronous elements (e.g., ?ops)have associated parameters such as setup, hold, clock frequency, and output valid times.
Keep in mind that each manufacturer has a somewhat different style of presentingthese speci?cations. The necessary information should exist, but data sheet sectionsmay be named differently; they may include certain information in different groupings,and terminology may be slightly different.
Speci?cations may be provided in mixed combinations of minimum, typical/nominal,and maximum. When a minimum or maximum limit is not speci?ed, it is understood tobe self-evi- dent or subject to a physical limitation that is beyond the scope of thedevice. Using Fairchilds 74LS00 as an example, no minimum output current isspeci?ed, because the physical minimum is very near zero. The actual output currentis determined by the load that is being driven, assum- ing that the load draws nomore than the speci?ed maximum. Other speci?cations are shown under certainoperating conditions. A well written data sheet provides guaranteed speci?cationsunder worst-case conditions. Here, the logic 1 output voltage (VOH) is speci?edas a minimum of 2.5 V under conditions of minimum supply voltage (VCC), maximumoutput current (IOH), and maximum logic-low input voltage (VIL). These areworst-case conditions. When VCC decreases, so will VOH. When IOH increases,it places a greater load on the output, dragging it down to its lowest level.
Timing speci?cations may also be incomplete. Manufacturers do not alwaysguarantee minimum or maximum parameters, depending on the speci?c type ofdevice and the particular speci?cation. As with DC voltages, worst-case parametersshould always be speci?ed. When a minimum or maximum delay is not speci?ed,it is generally because that parameter is of secondary importance, and themanufacturer was unable to control its process to a suf?cient level of detail toguarantee that value. In many situations where incomplete speci?cations are given,there are acceptable reasons for doing so, and the lack of information does nothurt the quality of the design.
Typical timing numbers are not useful in many circumstances, because they donot represent a limit of the devices operation. A thorough design must take intoaccount the best and worst perfor- mance of each IC in the circuit so that one canguarantee that the circuit will function under all conditions. Therefore, worst-casetiming parameters are usually the most important to consider ?rst, because theyare the dominant limit of a digital systems performance in most cases. In moreadvanced digital systems, minimum parameters can become equally asimportant because of the need to meet hold time and thereby ensure that a signaldoes not disappear too quickly before the driven IC can properly sense thesignals logic level.
Output timing speci?cations are often speci?ed with an assumed set of loadingconditions, be- cause the current drawn by the load has an impact on the outputdrivers ability to establish a valid logic level. A small load will enable the IC toswitch its output faster, because less current is de- manded of the output.A heavier load has the opposite effect, because it draws more current, whichplaces a greater strain on the output driver.
podle : E-book Complete_Digital_Design
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Březen 19, 2010

Common Variants Of The 7400 Family

Přidal: oprava  :  Kategorie: Integrovaných obvodů a 7400 Logické Rodiny
In the 1970s and 1980s, the 7400 family was commonly manufactured in abipolar semiconductor process that operated using a +5-V power supply andwas known as transistor-transistor logic (TTL). The discussion of the 7400 familythus far has included only the original +5-V bipolar type. The 7400s popularityand broad application to digital design has kept it relevant through manyimprovements in semiconductor process technology. As engineers learned tofabricate faster and more ef?- cient ICs, the 7400 was redesigned in manydifferent process generations beginning in the late 1960s. Some of the morecommon 7400 variants are brie?y discussed here.
The original 7400 discrete TTL logic family featured typical propagation delaysof 10 ns per gate and power consumption, also called power dissipation, ofapproximately 10 mW per gate. By mod- ern standards, the 7400s speed isrelatively slow, and its power dissipation is relatively high. Increasing systemcomplexity dictates deeper logic: more gates chained together to implement morecomplex Boolean functions. Each added level of logic adds at least another gatesworth of propaga- tion delay. At the same time, power consumption alsobecomes a problem. Ten milliwatts may not sound like a lot of power, but,when multiplied by several thousand gates, it represents a substantial designproblem in terms of both supplying a large quantity of power and cooling theradiated heat from digital systems.
Two notable bipolar variants of the 7400 are the 74LS and 74F families. The74LS, LS indicating low-power Schottky, has speed comparable to that of theoriginal 7400, but it dissipates roughly 20 percent of its power. The 74F, Findicating fast, is approximately 80 percent faster than the 7400 and reducespower consumption by almost half. Whether the concern is reducing poweror increasing speed, these two families are useful for applications requiring 5-Vbipolar technology.
CMOS technology began to emerge in the 1980s as a popular process forfabricating digital ICs as a result of its lower power consumption as comparedto bipolar. The low-power characteristics of CMOS logic stem from the factthat a FET requires essentially no current to keep it in an on or off state(unlike a BJT, which always draws some current when it is turned on). A CMOSgate, there- fore, will draw current only when it switches. For this reason, thepower consumption of a CMOS logic gate is extremely low in an idle, or quiescent,state and increases with the frequency at which it switches.
Several CMOS 7400 families were introduced, among them being the 74HCTand 74ACT, each of which has power consumption orders of magnitude less thanbipolar equivalents at low frequen- cies. Earlier CMOS versions of the 7400were not fully compatible with the bipolar devices, because of voltage thresholddifferences between the CMOS and bipolar processes. A typical TTL output isonly guaranteed to rise above 2.5 V, depending on output loading. In contrast,a typical 5-V CMOS input requires a minimum level of around 3 V to guaranteedetecting a logic 1. This inconsistency in voltage range causes a fundamentalproblem in which a TTL gate driving an ordinary CMOS gate cannot beguaranteed to operate in all situations. Both the 74HCT and 74ACT familiespossess the low-power bene?ts of CMOS technology and retain compatibilitywith bipolar ICs. A 74HCT device is somewhat slower than a 74LS equivalent,and the 74ACT is faster than a 74LS device.
There has been an explosion of 7400 variants. Most of the families introducedin the last decade are based on CMOS technology and are tailored to a broadset of applications ranging from simple speed to high-power bus drivers. Mosttypes of 7400 devices share common pin-outs and functions, with the exceptionof some proprietary specialized parts that may be produced by only a singlemanufacturer. Most of the 7400 families still require +5-V supplies, but lowervoltages such as 3.3 V, 2.5 V, 1.8 V, a 1.5 V are available as well. Theselower-voltage families are important because of the general trend toward lowervoltages for digital logic.
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Březen 18, 2010

Synchronous Logic Design With The 7400 Family

Přidal: oprava  :  Kategorie: Integrovaných obvodů a 7400 Logické Rodiny
The preceding LED driver example shows how state-less logic (logic without ?opsand a clock) can be designed to implement an arbitrary logic equation. State-fulllogic is almost always required in a digital system, because it is necessary to advanceone step at a time (one step each cycle) through an algorithm. Some 7400 ICs,such as counters, implement synchronous logic within the IC itself by combiningBoolean logic gates and ?ops on the same die. Other 7400 ICs implement only?ops that may be combined externally with logic to create the desired function.
An example of a synchronous logic application is a basic serial communicationscontroller. Serial communications is the process of taking parallel data, perhapsa byte of information, and transmit- ting or receiving that byte at a rate of onebit per clock cycle. The obvious downside of doing this is that it will take longerto transfer the byte, because it would be faster to just send the entire byte duringthe same cycle. The advantage of serial communications is a reduction in thenumber of wires re- quired to transfer information. Being able to string only afew wires between buildings instead of dozens usually compensates for theadded serial transfer time. If the time required to serially transfer bits is tooslow, the rate at which the bits are sent can be increased with some engineeringwork to achieve the desired throughput. Such speed improvements are beyondthe scope of this presentation. Real serial communications devices can get fairlycomplicated. For purposes of discussion, a fairly simplistic approach is taken.Once the decision is made to serialize a data byte, the problem arises of knowingwhen that byte begins and ends. Framing is the process of placing special patternsinto the data stream to indicate the start and end of data units. Without somemeans to frame the in- dividual bits as they are transmitted, the receiver would haveno means of ?nding the ?rst and last bits of each byte. In this example, a single startbit is used to mark the ?rst bit. Once the ?rst bit is detected,

FIGURE 2.13 LED driver logic using 74111 with fewer ICs.

OBR 2.13 LED driver logic using 74111 with fewer ICs.

The last bit is found by knowing that there are eight bits in a byte. During periodsof inactiv- ity, an idle communications interface is indicated by a persistent logic 0.When the transmitter is given a byte to send, it ?rst drives a logic-1 start bit andthen sends eight data bits. Each bit is sent in its own clock cycle. Therefore,nine clock cycles are required to transfer each byte. The serial interface is composedof two signals, clock and serial data, and functions as shown in Fig. 2.14.
The eight data bits are sent from least-signi?cant bit, bit 0, to most-signi?cant bit,bit 7, following the start bit. Following the transmission of bit 7, it is possible toimmediately begin a new byte by in- serting a new start bit. This timing diagramdoes not show a new start bit directly following bit 7. The corresponding outputof the receiver is shown in Fig. 2.15. Here, data out is the eight-bit quantity thathas been reconstructed from the serialized bit stream of Fig. 2.14. Readyindicates when data out is valid and is active-high.

FIGURE 2.14 Serial interface bit timing.

OBR 2.14 Serial interface bit timing.

FIGURE 2.15 Serial receive output timing.

OBR 2.15 Serial receive output timing.

All that is required of this receiver is to assemble the eight data bits in their properorder and then generate a ready signal. This ready signal lasts only one cycle, andany downstream logic waiting for the newly arrived byte must process it immediately.In a real system, a register might exist to capture the received byte when ready goesactive. This register would then pass the byte to the appropriate destination.This output timing shows two bytes transmitted back to back. They are separatedby nine cycles, because each byte requires an additional start bit for framing.
In contemplating the design of the receive portion of the serial controller, the needfor a serial-in/ parallel-out shift register becomes apparent to assemble the individualbits into a whole byte. Addi- tionally, some control logic is necessary to recognizethe start bit, wait eight clocks to assemble the incoming byte, and then generatea ready signal. This receiver has two basic states, or modes, of op- eration: idleand receiving. When idling, no start bit has yet been detected, so there is no usefulwork to be done. When receiving, a start bit has been observed, incoming bits areshifted into the shift reg- ister, and then a ready signal is generated. As soon as theready signal is generated, the receiver state may return to idle or remain in receivingif a new start bit is detected. Because there are two basic control logic states, thestate can be stored in a single ?ip-?op, forming a two-state ?nite state machine(FSM). An FSM is formed by one or more state ?ops with accompanying logicto generate a new state for the next clock cycle based on the current cycles state.The state is represented by the combined value of the state ?ops. An FSM with twostate ?ops can represent four unique states. Each state can represent a particularstep in an algorithm. The accompanying state logic controls the FSM by determiningwhen it is time to transition to a new piece of the algorithm a new state.
In the serial receive state machine, transitioning from idle to receiving can be doneaccording to the serial data input, which is 0 when inactive and 1 when indicatinga start bit. Transitioning back to idle must somehow be done nine cycles later.A counter could be used but would require some logic to sense a particular countvalue. Instead, a second shift register can be used to delay the start bit by ninecycles. When the start bit emerges from the last output bit in the shift register,the state machine can return to the idle state. Consider the logic in Fig. 2.16.The arrow-shaped boxes indicate connection points, or ports, of the circuit.
Under an idle condition, the input to the shift register is zero until the start bitappears at the data input, din. Nine cycles later, the ready bit emerges from theshift register. As soon as the start bit is observed, the state machine transitionsto the receiving state, changing the idle input to 0, effectively masking furtherinput to the shift register. This masking prevents nonzero data bits from enteringthe ready delay logic and causing false results.
Delaying the start bit by nine cycles solves one problem but creates another.The transition of the state machine back to idle is triggered by the emergenceof ready from the shift register. Therefore, this transition will actually occurten cycles after the start bit, because the state ?op, like all D ?ip- ?ops,requires a single cycle of latency to propagate its input to its output. Thisadditional cycle will prevent the control logic from detecting a new start bitimmediately following the last data bit of the byte currently in progress.A solution is to design ready with its nine-cycle delay and ready_next withan eight-cycle delay by tapping off one stage earlier in the shift register.In doing so, the state machine can look ahead one cycle into the future andreturn to idle in time for a new start bit that may be arriving. With the logicaldetails of the state machine now complete, the state machine can be representedwith the state transition diagram in Fig. 2.17.

FIGURE 2.16 Serial receive ready delay.

OBR 2.16 Serial receive ready delay.

A state transition diagram, often called a bubble diagram, shows all the states ofan FSM and the logical arcs that dictate how one state leads to another. Whenimplemented, the arcs are translated into the state logic to make the FSM function.With a clearly de?ned state transition diagram, the logic to drive the statemachine can be organized as shown in Table 2.3.

When in the idle state (1), a high on din (the start bit) must be observed to
transition to the receiv- ing state (0). Once in the receiving state, ready_next
must be high to return to idle. This logic is represented by the Boolean equation,

As with most problems, there exists more than one solution. Depending on thecomponents avail- able, one may choose to design the logic differently to makemore ef?cient use of those components. As a general rule, it is desirable to limitthe number of ICs used. The 7451 provides two AND-OR-INVERT gates,each of which implements the Boolean function,

This function is tantalizingly close to what is required for the state machine.It differs in that the in-version of two inputs (state and din) and a NOR functionrather than an OR are necessary. Both differences can be resolved using a 7404inverter IC, but there is a more ef?cient solution using the 74175 quad ?op.The 74175s four ?ops each provide both true and inverted outputs. Therefore, aseparate 7404 is not necessary. An inverted version of din can be obtained bypassing din through a ?ip-?op before feeding the remainder of the circuits logic.For purposes of notation, we will refer to this ?opped din as din?. Another ?opwill be used for the state machine. The inverted output of the state ?op willcompensate for the NOR vs. OR function of the 7451. A third ?op will formthe ninth bit of the ready delay shift register when combined with a 74164eight-bit parallel-out shift register.

FIGURE 2.17 Serial receive state machine.

OBR 2.17 Serial receive state machine.

Conveniently, the 74164 contains an internal AND gate at its input to implementthe idle-enable of the start bit into the shift register.
The total parts count for this serial receiver is four 7400-family ICs: two 74164shift registers, one 7451 AND-OR-INVERT, and one 74175 quad ?op. One ?opand one-half of the 7451 are unused in this application. OBR 2.18 shows howthese ICs are connected to implement the serial receive logic. Note that a mixed-styleof IC representation is used: most ICs are shown in a single block, but the 74175is broken into separate ?ops for clarity. Even if an IC is represented as a singleblock, it is not necessary to draw the individual pins in the order in which theyphysically appear. As with the previous example, the graphical representation of logicdepends on individual discretion. In addition to being functionally and electricallycorrect, a schematic diagram should be easy to understand.
All synchronous elements, the shift registers and ?ops, are driven by an input clocksignal, clk. The synchronous elements involved in the control path of the logic arealso reset at the beginning of operation with the active-low reset_ signal. Reset_ isnecessary to ensure that the state ?op and the ready_next delay logic begin in anidle state when power is ?rst applied. This is necessary, because ?ip-?ops powerup in a random, hence unknown, state. Once they are explicitly reset, they holdtheir state until the logic speci?cally changes their state. The shift register in thedata path, U3, does not require a reset, because its contents are not used untileight valid data bits are shifted in, thereby ?ushing the eight bits with randompower-up states. It would not hurt to connect U3s clr_ pin to reset_, but thisis not done to illustrate the option that is available. In certain logic implementations,adding reset capability to a ?op may incur a penalty in terms of additional cost orcircuit size. When a reset function is not free, it may be decided not to reset certain?ops if their contents do not need to be guaranteed at power up, as is the case here.

FIGURE 2.18 Serial receive logic schematic diagram.

OBR 2.18 Serial receive logic schematic diagram.

In this logic circuit, the inverted output of the state ?op, U1B, is used as the statebit to compen- sate for the 7451s NOR function. The unused clr_ and b pins of U3are connected to +5 V to render them neutral on the shift registers behavior. Theshift register will not clear itself, because clr_ is ac- tive-low and, similarly, theinternal input AND-gate that combines a and b, will be logically by-passed bytying b to logic 1. The parallel byte output of this serial receiver is designatedDout[7:0] and is formed by grouping the eight outputs of the shift register intoa single bus. One common nota- tion for assigning members of a bus is to connecteach individual member to a thicker line with some type of bus-ripper line. Thebus ripper is often drawn in the schematic diagram as mitered or curvedat the bus end to make its function more visually apparent.
Designing an accompanying serial transmitter follows a very similar design processto the preceding discussion. It is left as an exercise to the reader.

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