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The preceding LED driver example shows how state-less logic (logic without ?opsand a clock) can be designed to implement an arbitrary logic equation. State-fulllogic is almost always required in a digital system, because it is necessary to advanceone step at a time (one step each cycle) through an algorithm. Some 7400 ICs,such as counters, implement synchronous logic within the IC itself by combiningBoolean logic gates and ?ops on the same die. Other 7400 ICs implement only?ops that may be combined externally with logic to create the desired function.
An example of a synchronous logic application is a basic serial communicationscontroller. Serial communications is the process of taking parallel data, perhapsa byte of information, and transmit- ting or receiving that byte at a rate of onebit per clock cycle. The obvious downside of doing this is that it will take longerto transfer the byte, because it would be faster to just send the entire byte duringthe same cycle. The advantage of serial communications is a reduction in thenumber of wires re- quired to transfer information. Being able to string only afew wires between buildings instead of dozens usually compensates for theadded serial transfer time. If the time required to serially transfer bits is tooslow, the rate at which the bits are sent can be increased with some engineeringwork to achieve the desired throughput. Such speed improvements are beyondthe scope of this presentation. Real serial communications devices can get fairlycomplicated. For purposes of discussion, a fairly simplistic approach is taken.Once the decision is made to serialize a data byte, the problem arises of knowingwhen that byte begins and ends. Framing is the process of placing special patternsinto the data stream to indicate the start and end of data units. Without somemeans to frame the in- dividual bits as they are transmitted, the receiver would haveno means of ?nding the ?rst and last bits of each byte. In this example, a single startbit is used to mark the ?rst bit. Once the ?rst bit is detected,

The last bit is found by knowing that there are eight bits in a byte. During periodsof inactiv- ity, an idle communications interface is indicated by a persistent logic 0.When the transmitter is given a byte to send, it ?rst drives a logic-1 start bit andthen sends eight data bits. Each bit is sent in its own clock cycle. Therefore,nine clock cycles are required to transfer each byte. The serial interface is composedof two signals, clock and serial data, and functions as shown in Fig. 2.14.
The eight data bits are sent from least-signi?cant bit, bit 0, to most-signi?cant bit,bit 7, following the start bit. Following the transmission of bit 7, it is possible toimmediately begin a new byte by in- serting a new start bit. This timing diagramdoes not show a new start bit directly following bit 7. The corresponding outputof the receiver is shown in Fig. 2.15. Here, data out is the eight-bit quantity thathas been reconstructed from the serialized bit stream of Fig. 2.14. Readyindicates when data out is valid and is active-high.

All that is required of this receiver is to assemble the eight data bits in their properorder and then generate a ready signal. This ready signal lasts only one cycle, andany downstream logic waiting for the newly arrived byte must process it immediately.In a real system, a register might exist to capture the received byte when ready goesactive. This register would then pass the byte to the appropriate destination.This output timing shows two bytes transmitted back to back. They are separatedby nine cycles, because each byte requires an additional start bit for framing.
In contemplating the design of the receive portion of the serial controller, the needfor a serial-in/ parallel-out shift register becomes apparent to assemble the individualbits into a whole byte. Addi- tionally, some control logic is necessary to recognizethe start bit, wait eight clocks to assemble the incoming byte, and then generatea ready signal. This receiver has two basic states, or modes, of op- eration: idleand receiving. When idling, no start bit has yet been detected, so there is no usefulwork to be done. When receiving, a start bit has been observed, incoming bits areshifted into the shift reg- ister, and then a ready signal is generated. As soon as theready signal is generated, the receiver state may return to idle or remain in receivingif a new start bit is detected. Because there are two basic control logic states, thestate can be stored in a single ?ip-?op, forming a two-state ?nite state machine(FSM). An FSM is formed by one or more state ?ops with accompanying logicto generate a new state for the next clock cycle based on the current cycles state.The state is represented by the combined value of the state ?ops. An FSM with twostate ?ops can represent four unique states. Each state can represent a particularstep in an algorithm. The accompanying state logic controls the FSM by determiningwhen it is time to transition to a new piece of the algorithm a new state.
In the serial receive state machine, transitioning from idle to receiving can be doneaccording to the serial data input, which is 0 when inactive and 1 when indicatinga start bit. Transitioning back to idle must somehow be done nine cycles later.A counter could be used but would require some logic to sense a particular countvalue. Instead, a second shift register can be used to delay the start bit by ninecycles. When the start bit emerges from the last output bit in the shift register,the state machine can return to the idle state. Consider the logic in Fig. 2.16.The arrow-shaped boxes indicate connection points, or ports, of the circuit.
Under an idle condition, the input to the shift register is zero until the start bitappears at the data input, din. Nine cycles later, the ready bit emerges from theshift register. As soon as the start bit is observed, the state machine transitionsto the receiving state, changing the idle input to 0, effectively masking furtherinput to the shift register. This masking prevents nonzero data bits from enteringthe ready delay logic and causing false results.
Delaying the start bit by nine cycles solves one problem but creates another.The transition of the state machine back to idle is triggered by the emergenceof ready from the shift register. Therefore, this transition will actually occurten cycles after the start bit, because the state ?op, like all D ?ip- ?ops,requires a single cycle of latency to propagate its input to its output. Thisadditional cycle will prevent the control logic from detecting a new start bitimmediately following the last data bit of the byte currently in progress.A solution is to design ready with its nine-cycle delay and ready_next withan eight-cycle delay by tapping off one stage earlier in the shift register.In doing so, the state machine can look ahead one cycle into the future andreturn to idle in time for a new start bit that may be arriving. With the logicaldetails of the state machine now complete, the state machine can be representedwith the state transition diagram in Fig. 2.17.

A state transition diagram, often called a bubble diagram, shows all the states ofan FSM and the logical arcs that dictate how one state leads to another. Whenimplemented, the arcs are translated into the state logic to make the FSM function.With a clearly de?ned state transition diagram, the logic to drive the statemachine can be organized as shown in Table 2.3.

As with most problems, there exists more than one solution. Depending on thecomponents avail- able, one may choose to design the logic differently to makemore ef?cient use of those components. As a general rule, it is desirable to limitthe number of ICs used. The 7451 provides two AND-OR-INVERT gates,each of which implements the Boolean function,

This function is tantalizingly close to what is required for the state machine.It differs in that the in-version of two inputs (state and din) and a NOR functionrather than an OR are necessary. Both differences can be resolved using a 7404inverter IC, but there is a more ef?cient solution using the 74175 quad ?op.The 74175s four ?ops each provide both true and inverted outputs. Therefore, aseparate 7404 is not necessary. An inverted version of din can be obtained bypassing din through a ?ip-?op before feeding the remainder of the circuits logic.For purposes of notation, we will refer to this ?opped din as din?. Another ?opwill be used for the state machine. The inverted output of the state ?op willcompensate for the NOR vs. OR function of the 7451. A third ?op will formthe ninth bit of the ready delay shift register when combined with a 74164eight-bit parallel-out shift register.

Conveniently, the 74164 contains an internal AND gate at its input to implementthe idle-enable of the start bit into the shift register.
The total parts count for this serial receiver is four 7400-family ICs: two 74164shift registers, one 7451 AND-OR-INVERT, and one 74175 quad ?op. One ?opand one-half of the 7451 are unused in this application. Figure 2.18 shows howthese ICs are connected to implement the serial receive logic. Note that a mixed-styleof IC representation is used: most ICs are shown in a single block, but the 74175is broken into separate ?ops for clarity. Even if an IC is represented as a singleblock, it is not necessary to draw the individual pins in the order in which theyphysically appear. As with the previous example, the graphical representation of logicdepends on individual discretion. In addition to being functionally and electricallycorrect, a schematic diagram should be easy to understand.
All synchronous elements, the shift registers and ?ops, are driven by an input clocksignal, clk. The synchronous elements involved in the control path of the logic arealso reset at the beginning of operation with the active-low reset_ signal. Reset_ isnecessary to ensure that the state ?op and the ready_next delay logic begin in anidle state when power is ?rst applied. This is necessary, because ?ip-?ops powerup in a random, hence unknown, state. Once they are explicitly reset, they holdtheir state until the logic speci?cally changes their state. The shift register in thedata path, U3, does not require a reset, because its contents are not used untileight valid data bits are shifted in, thereby ?ushing the eight bits with randompower-up states. It would not hurt to connect U3s clr_ pin to reset_, but thisis not done to illustrate the option that is available. In certain logic implementations,adding reset capability to a ?op may incur a penalty in terms of additional cost orcircuit size. When a reset function is not free, it may be decided not to reset certain?ops if their contents do not need to be guaranteed at power up, as is the case here.

In this logic circuit, the inverted output of the state ?op, U1B, is used as the statebit to compen- sate for the 7451s NOR function. The unused clr_ and b pins of U3are connected to +5 V to render them neutral on the shift registers behavior. Theshift register will not clear itself, because clr_ is ac- tive-low and, similarly, theinternal input AND-gate that combines a and b, will be logically by-passed bytying b to logic 1. The parallel byte output of this serial receiver is designatedDout[7:0] and is formed by grouping the eight outputs of the shift register intoa single bus. One common nota- tion for assigning members of a bus is to connecteach individual member to a thicker line with some type of bus-ripper line. Thebus ripper is often drawn in the schematic diagram as mitered or curvedat the bus end to make its function more visually apparent.
Designing an accompanying serial transmitter follows a very similar design processto the preceding discussion. It is left as an exercise to the reader.