March 30, 2010
Most memory devices, whether volatile or nonvolatile, contain a single interfacethrough which their contents are accessed. In the context of a basic computersystem with a single microprocessor, this single-port architecture is well suited.There are some architectures in which multiple microprocessors or logic blocksrequire access to the same shared pool of memory. A shared pool of memorycan be constructed in a couple of ways. First, conventional DRAM or SRAMcan be combined with ex- ternal logic that takes requests from separate entities(e.g., microprocessors) and arbitrates access to one requestor at a time. Whenthe shared memory pool is large, and when simultaneous access by multiplerequesters is not required, arbitration can be an ef?cient mechanism. However,the complexity of arbitration logic may be excessive for small shared-memorypools, and arbitration does not enable simultaneous access. A means of sharingmemory without arbitration logic and with simultaneous access capability is toconstruct a true multiport memory element.
A multiport memory provides simultaneous access to multiple external entities.Each port may be read/write capable, read-only, or write-only depending onthe implementation and application. Multiport memories are generally kept relativelysmall, because their complexity, and hence their cost, increases signi?cantly asadditional ports are added, each with its own decode and control logic.Most multiport memories are dual-port elements as shown in Fig. 4.16.
A true dual-port memory places no restrictions on either ports transactions atany given time. It is the responsibility of the engineer to ensure that one requesterdoes not con?ict with the other. Con-?icts arise when one requester writes amemory location while the other is either reading or writing that same location.If a simultaneous read/write occurs, what data does the reader see? Is it the databefore or after the write? Likewise, if two writes proceed at the same time,which one wins? While these riddles could be worked out for speci?c applicationswith custom logic, it is safer not to worry about such corner cases. Instead,the system design should avoid such con?icts unless there is a strong reason tothe contrary.
One common application of a dual-port memory is sharing information betweentwo micropro- cessors as shown in Fig. 4.17. A dual-port memory sits betweenthe microprocessors and can be par- titioned into a separate message bin, ormemory area, for each side. Bin A contains messages written by CPU A andread by CPU B. Bin B contains messages written by CPU B and read by CPU A.Noti?cation of a waiting message is accomplished via a CPU interrupt, therebyreleasing the CPUs from having to constantly poll the memory as they wait formessages to arrive. The entire process might work as follows:
1. CPU A writes a message for CPU B into Bin A.2. CPU A asserts an interrupt to CPU B indicating the a message is waiting in Bin A.3. CPU B reads the message in Bin A.4. CPU B acknowledges the interrupt from CPU A.5. CPU A releases the interrupt to CPU B.
An implementation like this prevents dual-port memory con?icts because one CPUwill not read a message before it has been fully written by the other CPU and neitherCPU writes to both bins.
A multiport memory provides simultaneous access to multiple external entities.Each port may be read/write capable, read-only, or write-only depending onthe implementation and application. Multiport memories are generally kept relativelysmall, because their complexity, and hence their cost, increases signi?cantly asadditional ports are added, each with its own decode and control logic.Most multiport memories are dual-port elements as shown in Fig. 4.16.
A true dual-port memory places no restrictions on either ports transactions atany given time. It is the responsibility of the engineer to ensure that one requesterdoes not con?ict with the other. Con-?icts arise when one requester writes amemory location while the other is either reading or writing that same location.If a simultaneous read/write occurs, what data does the reader see? Is it the databefore or after the write? Likewise, if two writes proceed at the same time,which one wins? While these riddles could be worked out for speci?c applicationswith custom logic, it is safer not to worry about such corner cases. Instead,the system design should avoid such con?icts unless there is a strong reason tothe contrary.
One common application of a dual-port memory is sharing information betweentwo micropro- cessors as shown in Fig. 4.17. A dual-port memory sits betweenthe microprocessors and can be par- titioned into a separate message bin, ormemory area, for each side. Bin A contains messages written by CPU A andread by CPU B. Bin B contains messages written by CPU B and read by CPU A.Noti?cation of a waiting message is accomplished via a CPU interrupt, therebyreleasing the CPUs from having to constantly poll the memory as they wait formessages to arrive. The entire process might work as follows:
1. CPU A writes a message for CPU B into Bin A.2. CPU A asserts an interrupt to CPU B indicating the a message is waiting in Bin A.3. CPU B reads the message in Bin A.4. CPU B acknowledges the interrupt from CPU A.5. CPU A releases the interrupt to CPU B.
An implementation like this prevents dual-port memory con?icts because one CPUwill not read a message before it has been fully written by the other CPU and neitherCPU writes to both bins.
FIGURE 4.16 Dual-port memory.
FIGURE 4.17 Dual microprocessor message passing architecture.
By : E-book Complete_Digital_Design
