Март 03, 2010
Derived Logical Building Blocks
Публикувано от: ремонт : Категория: Цифрови Logic
Basic logic gates and ?ops can be combined to form more complex structures thatare treated as building blocks when designing larger digital systems. There are variouscommon functions that an engineer does not want to redesign from scratch each time.Some of the common building blocks are multiplexers, demultiplexers, tri-statebuffers, registers, and shift registers. Counters represent another building blockalluded to in the previous discussion of synchronous logic. A counter is acombination of ?ops and gates that can count either up or down, depending onthe implementation. Multiplexers, sometimes called selectors, are combinatorialelements that function as a multiposi- tion logical switches to select one of manyinputs. ФИГУРА 1.20 shows a common schematic representation of a multiplexer,often shortened to mux. A mux has an arbitrary number of data inputs, oftenan even power of two, and a smaller number of selector inputs. According tothe binary state of the selector inputs, a speci?c data input is transferred tothe output.
Muxes are useful, because logic circuits often need to choose between multipledata values. A counter, for example, may choose between loading a next countvalue or loading an arbitrary value from external logic. A possible truth table fora 4-to-1 mux is shown in Table 1.15. Each selector input value maps to one,and only one, data input.
Muxes are useful, because logic circuits often need to choose between multipledata values. A counter, for example, may choose between loading a next countvalue or loading an arbitrary value from external logic. A possible truth table fora 4-to-1 mux is shown in Table 1.15. Each selector input value maps to one,and only one, data input.
A demultiplexer, also called a demux, performs the inverse operation of a muxby transferring a single input to the output that is selected by select inputs.A demux is drawn similarly to a mux, , както е показано на фиг. 1.21.
ФИГУРА 1.20 Four-to-one multiplexer.
ФИГУРА 1.21 One-to-four demultiplexer.
A possible truth table for a 1-to-4 demux is shown in Table 1.16. Those outputsthat are not selected are held low. The output that is selected assumes the stateof the data input.
A popular use for a demux is as a decoder. The main purpose of a decoder is notso much to transfer an input to one of several outputs but simply to assert oneoutput while not asserting those that are not selected. This function has great utilityin microprocessor address decoding, which involves selecting one of multiple devices(e.g., a memory chip) at a time for access. The truth table for a 2-to-4 decoder isshown in Table 1.17. The decoders outputs are active-low, because most memoryand microprocessor peripheral chips use active-low enable signals.
Tri-state buffers are combinatorial elements that can drive three output statesrather than the standard 0 и 1 states. The third state is off, often referredto as high-impedance, hi-Z, or just Z. Tri-state buffers enable multipledevices to share a common output wire by cooperatively agreeing to haveonly one device drive the wire at any one time, during which all otherdevices remain in hi-Z. A tri-state buffer is drawn as shown in Fig. 1.22.
ФИГУРА 1.22 Tri-state buffer.
A tri-state buffer passes its D-input to Y-output when enabled. Otherwise,the output will be turned off as shown in Table 1.18. Electrically, tri-statebehavior allows multiple tri-state buffers to be connected to the same wirewithout contention. Contention normally results when multiple outputs areconnected together be- cause some want to drive high and some low. Thiscreates potentially damaging electrical contention (a short circuit). както и да е,if multiple tri-state buffers are connected, and only one at a time is enabled,there is no possibility of contention. The main advantage here is that digitalbuses in computers
can be arbitrarily expanded by adding more devices without the need to add a fullset of input or output signals each time a new device is added. In a logical context,a bus is a collection of wires that serve a common purpose. например, acomputers data bus might be eight wires that travel to- gether and collectivelyrepresent a byte of data. Electrical contention on a bus is often called a bus?ght.Schematically, multiple tri-state buffers might be drawn as shown in Fig. 1.23.Each tri-state buffer contains its own enable signal, which is usually driven bysome type of decoder. The decoder guarantees that only one tri-state bufferis active at any one time, preventing contention on the common wire.
Registers are collections of multiple ?ops arranged in a group with a commonfunction. They are a common synchronous-logic building block and are commonlyfound in multiples of 8-bit widths, thereby representing a byte, which is the mostcommon unit of information exchange in digital systems. An 8-bit register providesa common clock and clock enable for all eight internal ?ops. The clock enableallows external control of when the ?ops get reloaded with new D-input valuesand when they retain their current values. It is common to ?nd registers that havea built-in tri-state buffer, allowing them to be placed directly onto a shared buswithout the need for an additional tristate buffer component.
Whereas normal registers simply store values, synchronous elements called shiftregisters manipulate groups of bits. Shift registers exist in all permutations of serialand parallel inputs and outputs.
The role of a shift register is to somehow change the sequence of bits in an arrayof bits. This includes creating arrays of bits from a single bit at a time (serial input)or distributing an array of bits one bit at a time (serial output). A serial-in,parallel-out shift register can be implemented by chaining several ?opstogether as shown in Fig. 1.24.
Registers are collections of multiple ?ops arranged in a group with a commonfunction. They are a common synchronous-logic building block and are commonlyfound in multiples of 8-bit widths, thereby representing a byte, which is the mostcommon unit of information exchange in digital systems. An 8-bit register providesa common clock and clock enable for all eight internal ?ops. The clock enableallows external control of when the ?ops get reloaded with new D-input valuesand when they retain their current values. It is common to ?nd registers that havea built-in tri-state buffer, allowing them to be placed directly onto a shared buswithout the need for an additional tristate buffer component.
Whereas normal registers simply store values, synchronous elements called shiftregisters manipulate groups of bits. Shift registers exist in all permutations of serialand parallel inputs and outputs.
The role of a shift register is to somehow change the sequence of bits in an arrayof bits. This includes creating arrays of bits from a single bit at a time (serial input)or distributing an array of bits one bit at a time (serial output). A serial-in,parallel-out shift register can be implemented by chaining several ?opstogether as shown in Fig. 1.24.
ФИГУРА 1.23 Multiple tri-state buffers on a single wire.
ФИГУРА 1.24 Serial-in, parallel-out shift register.
On each rising clock edge, a new serial input bit is clocked into the ?rst ?op, andeach ?op in succession loads its new value based on its predecessors value.At any given time, the parallel output of an N-bit shift register re?ects the stateof the last N bits shifted in up to that time. In this example (N = 4), a serial streamof bits collected in four clock cycles can be operated upon as a unit of fourbits once every fourth cycle. As shown, data is shifted in MSB ?rst, becauseDout[3] is shown in the last bit position. Such a simple transformation is useful,because it is often more practical to communicate digital data in serial formwhere only one bit of information is sent per clock cycle, but impractical tooperate on that data serially. An advantage of serial communication is thatfewer wires are required as compared to parallel. Yet, parallel representationis important because arithmetic logic can get overly cumbersome if it has tokeep track of one bit at a time. A parallel-in, serial-out shift register is verysimilar, , както е показано на фиг. 1.25, with the signals connected for MSB ?rst opera-tion to match the previous example.
Four ?ops are used here as well. както и да е, instead of taking in one bit at a time,all ?ops are loaded when the load signal is asserted. The 2-to-1 muxes arecontrolled by the load signal and de- termine if the ?ops are loaded with newparallel data or shifted serial data. Over each of the next four clock cycles,the individual bits are shifted out one at a time. If these two shift register circuitswere connected together, a crude serial data communications link could becreated whereby parallel data is converted to serial and then back to parallelat each end.
Four ?ops are used here as well. както и да е, instead of taking in one bit at a time,all ?ops are loaded when the load signal is asserted. The 2-to-1 muxes arecontrolled by the load signal and de- termine if the ?ops are loaded with newparallel data or shifted serial data. Over each of the next four clock cycles,the individual bits are shifted out one at a time. If these two shift register circuitswere connected together, a crude serial data communications link could becreated whereby parallel data is converted to serial and then back to parallelat each end.
ФИГУРА 1.25 Parallel-in, serial-out shift register.
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