المسيرة 27, 2010
Static RAM, or SRAM, is the most basic and easy to use type of volatile memoryand is found in almost every computer in one form or another. An SRAM deviceis conceptually easy to understand, consisting of an array of latches along withcontrol and decode logic to resolve the address that is being read or written atany given time. Each latch is a feedback circuit that traps and maintains aparticular logic state. A typical SRAM bit implementation is shown in Fig. 4.7.
FIGURE 4.7 SRAM bit feedback latch.
An SRAM latch is created by connecting two inverters in a loop. One side of theloop remains sta- ble at the desired logic state, and the other remains stable at theopposite state. Inverters are used rather than noninverting buffers, because aninverter is the simplest logic element to construct. The two pass transistors oneither side of the latch enable both writing and reading. When writing, the transistorsturn on and force each half of the loop to whatever state is driven on the verticalbit lines. When reading, the transistors also turn on, but the bit lines are sensedrather than driven. Typical SRAM implementations require six transistors per bitof memory: two transistors for each inverter and the two pass transistors. Someimplementations use only a single transistor per inverter, requiring only fourtransistors per bit.
Discrete asynchronous SRAM devices have been around for decades. In the 1980s,أل 6264 and 62256 were manufactured by multiple vendors and used in applicationsthat required simple RAM architectures with relatively quick access times and lowpower consumption. The 62xxx family is numbered according to its density inkilobits. Hence, أل 6264 provides 65,536 bits of RAM ar- ranged as 8k ? 8.The 62256 provides 262,144 bits of RAM arranged as 32k ? 8. Beingmanufactured in CMOS technology and not using a clock, these devicesconsume very little power and draw only microamps when not being accessed.
The 62xxx family pin assignment is virtually identical to that of the 27xxx EPROMfamily, enabling system designs where either EPROM or SRAM can be substitutedinto the same location with only a couple of jumpers to set for unique signals suchas the program-enable on an EPROM or write-enable on an SRAM. Like anEPROM or basic ?ash device, asynchronous SRAMs have a simple interfaceconsisting of address, data, chip select, output enable, and write enable. Thisinterface is shown in Fig. 4.8.
Writes are performed whenever the WE* signal is held low. Therefore, one mustensure that the desired address and data are stable before asserting WE* andthat WE* is removed while address and data remain stable. Otherwise, thewrite may corrupt an undesired memory location. Unlike an EPROM, but like?ash, the data bus is bidirectional during normal operation. أل ?rst twotransactions shown are writes as evidenced by the separate assertions ofWE* for the duration of address and data stability. As soon as the writesare completed, the microprocessor should release the data bus to thehigh-impedance state. When OE* is asserted, the SRAM begins driving thedata bus and the output re?ects the data contents at the locations speci?edon the address bus.
Asynchronous SRAMs are available with access times of less than 100 ns forinexpensive parts and down to 10 ns for more expensive devices. Access timemeasures both the maximum delay between a stable read address and itscorresponding data and the minimum duration of a write cycle. Their ease ofuse makes them suitable for small systems where megabytes of memory arenot re-quired and where reduced complexity and power consumption arekey requirements. Volatile memory doesnt get any simpler than asynchronousSRAM.
Prior to the widespread availability of ?ash, many computer designs in the 1980sutilized asyn- chronous SRAM with a battery backup as a means of implementingnonvolatile memory for storing con?guration information. Because an idle SRAMdraws only microamps of current, a small battery can maintain an SRAMscontents for several years while the main power is turned off. Using SRAM inthis manner has two distinct advantages over other technologies: writes arequick and easy, because there are no complex EEPROM or ?ash programmingalgorithms, and there is no limit to the number of write cycles performed overthe life of the product. The downsides to this approach are a lack of securityfor protecting valuable con?guration information and the need for a battery tomaintain the memory contents. Requiring a battery increases the complexity ofthe system and also begs the question of what happens when the battery wearsout. In the 1980s, it was common for a PCs BIOS con?guration to be storedin battery-backed CMOS SRAM. This is how terms like the CMOS andCMOS setup entered the lexicon of PC administration.
Discrete asynchronous SRAM devices have been around for decades. In the 1980s,أل 6264 and 62256 were manufactured by multiple vendors and used in applicationsthat required simple RAM architectures with relatively quick access times and lowpower consumption. The 62xxx family is numbered according to its density inkilobits. Hence, أل 6264 provides 65,536 bits of RAM ar- ranged as 8k ? 8.The 62256 provides 262,144 bits of RAM arranged as 32k ? 8. Beingmanufactured in CMOS technology and not using a clock, these devicesconsume very little power and draw only microamps when not being accessed.
The 62xxx family pin assignment is virtually identical to that of the 27xxx EPROMfamily, enabling system designs where either EPROM or SRAM can be substitutedinto the same location with only a couple of jumpers to set for unique signals suchas the program-enable on an EPROM or write-enable on an SRAM. Like anEPROM or basic ?ash device, asynchronous SRAMs have a simple interfaceconsisting of address, data, chip select, output enable, and write enable. Thisinterface is shown in Fig. 4.8.
Writes are performed whenever the WE* signal is held low. Therefore, one mustensure that the desired address and data are stable before asserting WE* andthat WE* is removed while address and data remain stable. Otherwise, thewrite may corrupt an undesired memory location. Unlike an EPROM, but like?ash, the data bus is bidirectional during normal operation. أل ?rst twotransactions shown are writes as evidenced by the separate assertions ofWE* for the duration of address and data stability. As soon as the writesare completed, the microprocessor should release the data bus to thehigh-impedance state. When OE* is asserted, the SRAM begins driving thedata bus and the output re?ects the data contents at the locations speci?edon the address bus.
Asynchronous SRAMs are available with access times of less than 100 ns forinexpensive parts and down to 10 ns for more expensive devices. Access timemeasures both the maximum delay between a stable read address and itscorresponding data and the minimum duration of a write cycle. Their ease ofuse makes them suitable for small systems where megabytes of memory arenot re-quired and where reduced complexity and power consumption arekey requirements. Volatile memory doesnt get any simpler than asynchronousSRAM.
Prior to the widespread availability of ?ash, many computer designs in the 1980sutilized asyn- chronous SRAM with a battery backup as a means of implementingnonvolatile memory for storing con?guration information. Because an idle SRAMdraws only microamps of current, a small battery can maintain an SRAMscontents for several years while the main power is turned off. Using SRAM inthis manner has two distinct advantages over other technologies: writes arequick and easy, because there are no complex EEPROM or ?ash programmingalgorithms, and there is no limit to the number of write cycles performed overthe life of the product. The downsides to this approach are a lack of securityfor protecting valuable con?guration information and the need for a battery tomaintain the memory contents. Requiring a battery increases the complexity ofthe system and also begs the question of what happens when the battery wearsout. In the 1980s, it was common for a PCs BIOS con?guration to be storedin battery-backed CMOS SRAM. This is how terms like the CMOS andCMOS setup entered the lexicon of PC administration.
FIGURE 4.8 62xxx SRAM interface.
SRAM is implemented not only as discrete memory chips but is commonly foundintegrated within other types of chips, including microprocessors. Smallermicroprocessors or microcontrollers (microprocessors integrated with memoryand peripherals on a single chip) often contain a quantity of on-board SRAM.More complex microprocessors may contain on-chip data caches implementedwith SRAM.
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