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The preceding timing analysis example is simpli?ed for ease of presentation by
assuming that the source and destination ?ops in a logic path are driven by the
same clock signal. Although a synchro- nous circuit uses a common clock for
all ?ops, there are small, nonzero variances in clock timing at individual ?ops.
Wiring delay variances are one source of this nonideal behavior. When a clock
source drives two ?ops, the two wires that connect to each ?ops clock input are
usually not identical

FIGURE 1.16 Hypothetical logic circuit.

in length. This length inequality causes one ?ops clock to arrive slightly before or
after the other ?ops clock.

Clock skew is the term used to characterize differences in edge timing between
multiple clock inputs. Skew caused by wiring delay variance can be effectively
minimized by designing a circuit so that clock distribution wires are matched in length.
A more troublesome source of clock skew arises when there are too many clock
loads to be driven by a single source. Multiple clock drivers are necessary in these
situations, with small variations in electrical characteristics between each driver.
These driver variances result in clock skew across all the ?ops in a synchronous
design. As might be expected, clock skew usually reduces the frequency at which
a synchronous circuit can operate. Clock skew is subtracted from the nominal
clock period for setup time analysis purposes, because the worst-case scenario
shown in Fig. 1.17 must be considered. This scenario uses the same logic circuit in
Fig. 1.16 but shows two separate clocks with 1 ns of skew between them.

The worst timing occurs when the destination ?ops clock arrives before that of the
source ?op, thereby reducing the amount of time available for the D-input to stabilize.
Instead of the circuit having zero margin with a 20-ns period, clock skew increases
the minimum period to 21 ns. The extra 1 ns compensates for the clock skew to
restore a minimum source to destination period time of 20 ns. A slower circuit
such as this one is not very sensitive to clock skew, especially after backing off to
40 MHz for timing margin as shown previously. Digital systems that run at relatively
low frequencies may not be affected by clock skew, because they often have
substantial margins built into their timing analyses. As clock speeds increase, the
margin decreases to the point at which clock skew and interconnect delay become
important limiting factors in system design.

Hold time compliance can become more dif?cult in the presence of clock skew.
The basic problem occurs when clock skew reduces the source ?ops apparent t_CO
from the destination ?ops perspective, causing the destinations input to change
before t_H is satis?ed. Such problems are more prone in high-speed systems,
but slower systems are not immune. Figure 1.18 shows a timing diagram for a
circuit with 1 ns of clock skew where two ?ops are connected by a short wire
with nearly zero propagation delay. The ?ops have t_CO = 2 ns and t_H = 1.5 ns.
A scenario like this may be expe- rienced when connecting two chips that are
next to each other on a circuit board. In the absence of clock skew, the
destination ?ops input would change t_CO after the rising clock edge, exceeding t_H
by 0.5 ns. The worst-case clock skew causes the source ?op clock to arrive
before that of the destination ?op, resulting in an input change just 1 ns after the
rising clock edge and violating t_H. Solutions to skew-induced t_H violations include
reducing the skew or increasing the delay be- tween source and destination.
Unfortunately, increasing a signals propagation delay may cause t_SU
violations in high-speed systems.

FIGURE 1.17 Clock skew in?uence on setup time analysis.

FIGURE 1.18 Hold-time violation caused by clock skew.

Hold time may not be a problem in slower circuits, because slower circuits often
have paths between ?ops with suf?ciently long propagation delays to offset
clock skew problems. However, even slow circuits can experience hold-time
problems if ?ops are connected with wires or components that have small
propagation delays. It is also important to remember that hold-time compliance
is not a function of clock period but of clock skew, t_CO, and t_H. Therefore, a
slow system that uses fast components may have problems if the clock skew
exceeds the difference between t_CO and t_H.

By : E-book Complete_Digital_Design

Logic elements, including ?ip-?ops and gates, are physical devices that have ?nite
response times to stimuli. Each of these elements exhibits a certain propagation delay
between the time that an input is presented and the time that an output is generated.
As more gates are chained together to create more complex logic functions, the
overall propagation delay of signals between the end points increases. Flip-?ops are
triggered by the rising edge of a clock to load their new state, requiring that the input
to the ?ip-?op is stable prior to the rising edge. Similarly, a ?ip-?ops output stabilizes
at a new state some time after the rising edge. In between the output of a ?ip-?op
and the input of another ?ip-?op is an arbitrary collection of logic gates, as seen in
the preceding synchronous counter circuit. Synchronous timing analysis is the study
of how the various delays in a synchronous circuit combine to limit the speed at which
that circuit can operate. As might be expected, circuits with lesser delays are
able to run faster.

A clock breaks time into discrete intervals that are each the duration of a single
clock period. From a timing analysis perspective, each clock period is identical to
the last, because each rising clock edge is a new ?op triggering event. Therefore,
timing analysis considers a circuits delays over one clock period, between
successive rising (or falling) clock edges. Knowing that a wide range of clock
frequencies can be applied to a circuit, the question of time arises of how fast the
clock can go before the circuit stops working reliably. The answer is that the clock
must be slow enough to allow suf?cient time for the output of a ?op to stabilize,
for the signal to propagate through the combinatorial logic gates, and for the input
of the destination ?op to stabilize. The clock must also be slow enough for the ?op
to reliably detect each edge. Each ?op circuit is characterized by a minimum
clock pulse width that must be met. Failing to meet this minimum time can result in
the ?op missing clock events.

Timing analysis revolves around the basic timing parameters of a ?op: input setup
time (t_SU), input hold time (t_H), and clock-to-out time (t_CO). Setup time speci?es
the time immediately preceding the rising edge of the clock by which the input must
be stable. If the input changes too soon before the clock edge, the electrical circuitry
within the ?op will not have enough time to properly recognize the state of the input.
Hold time places a restriction on how soon after the clock edge the input

may begin to change. Again, if the input changes too soon after the clock edge, it
may not be properly detected by the circuitry. Clock-to-out time speci?es how
soon after the clock edge the output will be updated to the state presented at the
input. These parameters are very brief in duration and are usually measured in
nanoseconds. One nanosecond, abbreviated ns, is one billionth of a second.
In very fast microchips, they may be measured in picoseconds, or one trillionth
or a second. Consistent terminology is necessary when conducting timing analysis.
Timing is expressed in units of both clock frequency and time. Clock frequency,
or speed, is quanti?ed in units of hertz, named after the twentieth century German
physicist, Gustav Hertz. One hertz is equivalent to one clock cycle per second
one transition from low to high and a second transition from high to low. Units of
hertz are abbreviated as Hz and are commonly accompanied by pre?xes that denote
an order of magnitude. Commonly observed pre?xes used to quantify clock
frequency and their de?ni- tions are listed in Table 1.13. Unlike quantities of bytes
that use binary-based units, clock frequency uses decimal-based units.

Units of time are used to express a clocks period as well as basic logic element
delays such as the aforementioned t_SU, t_H, and t_CO. As with frequency, standard
pre?xes are used to indicate the order of magnitude of a time speci?cation. However,
rather than expressing positive powers of ten, the exponents are negative.
Table 1.14 lists the common time magnitude pre?xes employed in timing analysis.

Aside from basic ?op timing characteristics, timing analysis must take into
consideration the ?nite propagation delays of logic gates and wires that
connect ?op outputs to ?op inputs. All real components have nonzero
propagation delays (the time required for an electrical signal to move from an
input to an output on the same component). Wires have an approximate
propagation delay of 1 ns for every 6 in of length. Logic gates can have
propagation delays ranging from more than 10 ns down to the picosecond range,
depending on the technology being used. Newly designed logic circuits should
be analyzed for timing to ensure that the inherent propagation delays of the logic
gates and interconnect wiring do not cause a ?ops t_SU and t_H speci?cations to
be violated at a given clock frequency.

Basic timing analysis can be illustrated with the example logic circuit shown
Fig. 1.16. There are two ?ops connected by two gates. The logic inputs shown
unconnected are ignored in this instance, because timing analysis operates on a
single path at a time. In reality, other paths exist through these unconnected inputs,
and each path must be individually analyzed. Each gate has a ?nite propagation
delay, t_PROP , which is assumed to be 5 ns for the sake of discussion. Each ?op
has t_CO = 7 ns, t_SU = 3 ns, and t_H = 1 ns. For simplicity, it is assumed that there
is zero delay through the wires that connect the gates and ?ops.

The timing analysis must cover one clock period by starting with one rising clock
edge and ending with the next rising edge. How fast can the clock run? The ?rst
delay encountered is t_CO of the source ?op. This is followed by t_PROP of the two
logic gates. Finally, t_SU of the destination ?op must be met. These parameters
may be summed as follows:

t_CLOCK = t_CO + 2 ? t_PROP + t_SU = 20 ^_ns

The frequency and period of a clock are inversely related such that F = 1/t. A 20-ns
clock period corresponds to a 50-MHz clock frequency: 1/(20 ? 10⁹) = 50 ? 10⁶.
Running at exactly the calculated clock period leaves no room for design margin.
Increasing the period by 5 ns reduces the clock to 40 MHz and provides headroom
to account for propagation delay through the wires.

Hold time compliance can be veri?ed following setup time analysis. Meeting a ?ops
hold time is often not a concern, especially in slower circuits as shown above.
The 1 ns t_H speci?cation is easily met, because the destination ?ops D-input will
not change until t_CO + 2 ? t_PROP = 17 ns after the rising clock edge. Actual
timing parameters have variance associated with them, and the best-case
t_CO and t_PROP would be somewhat smaller numbers. However, there is so
much margin in this case that t_H compliance is not a concern.

Hold-time problems sometimes arise in fast circuits where t_CO and t_PROP
are very small. When there are no logic gates between two ?ops, t_PROP can
be nearly zero. If the minimum t_CO is nearly equal to the maximum t_H, the
situation should be carefully investigated to ensure that the destination
?ops input remains stable for a suf?cient time period after the active clock edge.

By : E-book Complete_Digital_Design

Today’s CRT monitors (those with television-like picture tubes) can handle the highest settings computer users are likely to want to use. If you run into a situation, however, in which an old monitor is displaying unusable video, it is possible that the Windows video settings exceed the capabilities of the monitor. You will have to diagnose the source of the problem. If you are able to read the text that appears on screen as the system is starting but the video becomes distorted and unreadable once Windows starts up, then the settings are most likely too high for the monitor. If the image is distorted from the moment you start up the computer, then it is possibly a video adapter issue. If it is the former, you will have to start Windows in Safe Mode, which will give you basic settings that almost all monitors will work with. While in Safe Mode, set the Display Properties to a lower setting and restart Windows. At this point, you might very well decide to get a new monitor that can display higher settings rather than live with a low resolution. You can try to find the monitor’s specifications on the Web and set the Display Properties accordingly. If you can’t find this information, which is possible, you’ll have to try lower settings until you find a combination that works.

The monitor itself will have settings for shape and size of the picture, brightness and contrast, and others. In addition, virtually all monitors manufactured for the last several years have an energy saving system. When the video signal from the computer stops, the monitor goes into a low-power state, and the power indicator light begins to blink or turns from green to orange. Some monitors, however, show a test pattern or no-video message in certain circumstances such as when the power comes back on after a failure and the computer is still off.